IDT49FCT3805BQG IDT, Integrated Device Technology Inc, IDT49FCT3805BQG Datasheet - Page 6
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IDT49FCT3805BQG
Manufacturer Part Number
IDT49FCT3805BQG
Description
IC BUFFER/CLK DVR 3.3V 20-QSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
49FCTr
Type
Fanout Buffer (Distribution)r
Datasheet
1.IDT49FCT3805BQ8.pdf
(7 pages)
Specifications of IDT49FCT3805BQG
Number Of Circuits
2
Ratio - Input:output
1:5
Differential - Input:output
No/No
Input
TTL
Output
TTL
Frequency - Max
166MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-QSOP
Frequency-max
166MHz
Number Of Outputs
10
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Propagation Delay Time
5ns
Operating Supply Voltage (min)
3V
Mounting
Surface Mount
Pin Count
20
Operating Supply Voltage (typ)
3.3V
Package Type
QSOP
Quiescent Current
10uA
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
49FCT3805BQG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT49FCT3805BQGI
Manufacturer:
IDT
Quantity:
5 064
TEST CIRCUITS AND WAVEFORMS
OUTPUT
IDT49FCT3805B
3.3V CMOS BUFFER/CLOCK DRIVER
OUTPUT
NORMALLY
NORMALLY
CONTROL
Generator
INPUT
OUTPUT
OUTPUT
INPUT
Pulse
INPUT
HIGH
LOW
SWITCH
CLOSED
SWITCH
OPEN
ENABLE
V
IN
t
t
Test Circuits for All Outputs
PZL
PZH
t
PLH
t
Output Skew - t
Pulse Skew - t
PLH
t
R
SK(p)
Package Delay
T
t
R
1.5V
1.5V
3.5V
0V
D.U.T.
V
= |t
CC
PHL -
t
PHZ
DISABLE
t
V
SK(P)
PLH
OUT
SK(X)
t
PHL
t
t
PHL
PLZ
|
t
F
0.3V
0.3V
50pF
0.8V
2.0V
V
1.5V
3V
1.5V
0V
V
3V
1.5V
0V
3.5V
V
0V
V
OH
OL
OH
OL
3V
1.5V
0V
500
500
V
1.5V
V
OL
OH
GND
6V
6
SWITCH POSITION
DEFINITIONS:
C
R
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; t
L
T
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
OUTPUT 1
OUTPUT 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
INPUT
PACKAGE 1
PACKAGE 2
Disable HIGH
Enable HIGH
Disable LOW
Enable LOW
OUTPUT
OUTPUT
INPUT
Test
t
SK(o)
t
SK(t)
= |t
Package Skew - t
Output Skew - t
= |t
t
PLH2 -
PLH1
t
PLH2
PLH2 -
t
SK(o)
t
t
PLH1
PLH1
t
t
PLH2
PLH1
t
|
SK(t)
or
F
t
|
OUT
|t
PHL1
SK(O)
or
≤ 2.5ns; t
PHL2 -
t
SK(T)
PHL2
t
|t
of the Pulse Generator.
SK(o)
PHL2 -
t
PHL1
t
t
PHL1
PHL2
R
Switch
GND
t
t
≤ 2.5ns
6V
SK(t)
PHL1
|
V
3V
1.5V
0V
V
1.5V
V
V
1.5V
|
OL
OH
OL
OH
V
V
V
3V
1.5V
0V
1.5V
1.5V
V
OH
OL
OH
OL