ICS85354AK-01LFT IDT, Integrated Device Technology Inc, ICS85354AK-01LFT Datasheet - Page 12
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ICS85354AK-01LFT
Manufacturer Part Number
ICS85354AK-01LFT
Description
IC MUX DUAL 2:1 1:2 16-VFQFPN
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Multiplexerr
Datasheet
1.ICS85354AK-01LFT.pdf
(18 pages)
Specifications of ICS85354AK-01LFT
Number Of Circuits
2
Ratio - Input:output
2:1, 1:2
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL
Output
LVPECL
Frequency - Max
2.5GHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-VFQFN
Frequency-max
2.5GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
85354AK-01LFT
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50
85354AK-01
RTT =
ERMINATION FOR
((V
FOUT
F
OH
IGURE
+ V
OL
3A. LVPECL O
) / (V
1
3.3V LVPECL O
CC
Z
Z
– 2)) – 2
transmission lines. Matched imped-
o
o
= 50
= 50
Z
o
50
UTPUT
T
ERMINATION
RTT
UTPUTS
50
PRELIMINARY
V
CC
FIN
- 2V
D
12
IFFERENTIAL
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT
F
IGURE
-
TO
3B. LVPECL O
-LVPECL/ECL M
Z
Z
o
o
= 50
= 50
125
84
ICS85354-01
UTPUT
3.3V
T
125
84
ERMINATION
D
REV. A JANUARY 16, 2008
UAL
ULTIPLEXER
FIN
2:1/1:2