ICS889872AKLFT IDT, Integrated Device Technology Inc, ICS889872AKLFT Datasheet - Page 2

• Manufacturer Part Number: ICS889872AKLFT
• Description: IC BUFFER/DIVIDER HS 16-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of ICS889872AKLFT

• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVDS
• Frequency - Max: 2GHz
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VFQFN
• Frequency-max: 2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 889872AKLFT

Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Symbol
R
ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PULLUP
Number
15, 16
7, 14
1, 2
3, 4
5, 6
10
11
12
13
8
9
Parameter
Input Pullup Resistor
QB0, nQB0
QB1, nQB1
nDISABLE
nRESET/
QA, nQA
V
S1, S0
Name
REF_AC
GND
V
nIN
V
IN
DD
T
Output
Output
Output
Output
Power
Power
Input
Input
Input
Input
Input
Type
Pullup
Pullup
Test Conditions
Description
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB0/nQB0).
LVDS interface levels.
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB1nQB1).
LVDS interface levels.
Differential undivided output pair. LVDS interface levels.
Power supply pins.
Output reset and enable/disable pin. When LOW, resets the divider select,
and align Bank A and Bank B edges. In addition, when LOW, Bank A and
Bank B will be disabled. Input threshold is V
Includes a 37k
Inverting differential LVPECL clock input. RT = 50
Reference voltage for AC-coupled applications. Equal to V
(approx.). Maximum sink/source current is 0.5mA.
Termination input. Leave pin floating.
Non-inverting LVPECL differential clock input.
RT = 50
Power supply ground.
Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB.
Input threshold is VDD/2. 37kW pullup resistor.
LVCMOS/LVTTL interface levels.
Ω
2
termination to V
Ω
pullup resistor. LVTTL / LVCMOS interface levels.
T
.
Minimum
Typical
DD
ICS889872AK REV. B JULY 10, 2008
37
/2V.
Ω
termination to V
Maximum
DD
PRELIMINARY
– 1.4V
T
.
Units
k
Ω