ICS889874AKLFT IDT, Integrated Device Technology Inc, ICS889874AKLFT Datasheet

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ICS889874AKLFT

Manufacturer Part Number
ICS889874AKLFT
Description
IC BUFFER/DIVIDER 1:2 16-VFQFPN
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Divider, Multiplexerr
Datasheet

Specifications of ICS889874AKLFT

Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL
Output
LVPECL
Frequency - Max
2.5GHz
Voltage - Supply
2.375 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-VFQFN
Frequency-max
2.5GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
889874AKLFT
B
nRESET
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
889874AK
G
which allows the device to be used as either a 1:2 fanout
buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several
differential signal types while minimizing the number of
required external components. The device is packaged in
a small, 3mm x 3mm VFQFN package, making it ideal for
use on space-constrained boards.
HiPerClockS™
IC S
V
LOCK
REF_AC
ENERAL
nIN
S2
S0
S1
IN
V
T
D
The ICS889874 is a high speed 1:2 Differential-
to-LVPECL Buffer/Divider and is a member of
the HiPerClockS
clock solutions from ICS. The ICS889874 has
a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider,
Decoder
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
Enable
FF
family of high performance
00 ÷2
01 ÷4
10 ÷8
11 ÷16
Enable
MUX
www.icst.com/products/hiperclocks.html
PRELIMINARY
0
1
1
F
• Two LVPECL outputs
• Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16
• IN, nIN input can accept the following differential input levels:
• Output frequency: > 2.5GHz
• Output skew: 5ps (typical)
• Part-to-part skew: TBD
• Additive jitter, RMS: <0.03ps (design target)
• Supply voltage range: (LVPECL), 2.375V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
D
LVPECL, LVDS, CML
Supply voltage range: (ECL), -3.465V to -2.375V
packages
EATURES
IFFERENTIAL
Q0
nQ0
Q1
nQ1
-
TO
-LVPECL B
P
3mm x 3mm x 0.95 package body
IN
nQ0
nQ1
Q0
Q1
A
16-Lead VFQFN
1
2
3
4
SSIGNMENT
ICS889874
16 15 14 13
5
K Package
ICS889874
Top View
6
UFFER
7
REV. A MARCH 20, 2006
8
12
11
10
9
/D
IN
V
V
nIN
T
REF
IVIDER
_
AC
1:2

Related parts for ICS889874AKLFT

ICS889874AKLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS889874 is a high speed 1:2 Differential to-LVPECL Buffer/Divider and is a member of HiPerClockS™ the HiPerClockS ™ family of high performance clock solutions from ICS. The ICS889874 has ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc ABLE ONTROL NPUT UNCTION ...

Page 4

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage, V -0.5V to +4.0V CC Inputs, V -0. Outputs Continuous Current Surge Current Input Current IN, nIN ±50mA V Current, I ±100mA T ...

Page 5

Integrated Circuit Systems, Inc. T 4D. LVPECL DC C ABLE HARACTERISTICS ...

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Integrated Circuit Systems, Inc. P ARAMETER LVPECL V EE -0.375V to -1.63V UTPUT OAD EST IRCUIT nQx PART 1 Qx nQy PART 2 Qy tsk(pp ART TO ART ...

Page 7

Integrated Circuit Systems, Inc. 3.3V LVPECL I B NPUT WITH UILT The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V and V must meet the V SWING OH PP ments. ...

Page 8

Integrated Circuit Systems, Inc. 2.5V LVPECL I B NPUT WITH UILT The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V and V must meet the V SWING OH requirements.Figures 3A ...

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Integrated Circuit Systems, Inc. 3. IFFERENTIAL NPUT WITH To prevent oscillation and to reduce noise recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 4. ...

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Integrated Circuit Systems, Inc ECOMMENDATIONS FOR NUSED I : NPUTS LVCMOS ONTROL INS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A ...

Page 11

Integrated Circuit Systems, Inc. T 2.5V LVPECL O ERMINATION FOR Figure 7A and Figure 7B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to ter- minating 50Ω 2V. For V = 2.5V, the ...

Page 12

Integrated Circuit Systems, Inc. θ ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS889874 is: 326 Pin compatible with SY89874U 889874AK ...

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Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR Ind ex Area View D Chamfer 4x 0.6 x 0.6 max OPTIONAL T ABLE Reference Document: JEDEC Publication 95, MO-220 889874AK PRELIMINARY ...

Page 14

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

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