ICS85314BGI-01LFT IDT, Integrated Device Technology Inc, ICS85314BGI-01LFT Datasheet
ICS85314BGI-01LFT
Specifications of ICS85314BGI-01LFT
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ICS85314BGI-01LFT Summary of contents
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G D ENERAL ESCRIPTION The ICS85314I- low skew, high performance 1-to-5 Differential-to-2.5V/3.3V LVPECL Fanout Buffer.The ICS85314I-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standarddifferential input levels. The single-ended CLK1 can accept LVCMOS or ...
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ABLE IN ESCRIPTIONS ...
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T 3A ABLE ONTROL NPUT UNCTION ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance Lead TSSOP 20 Lead SOIC Storage Temperature, T STG T 4A ...
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T 4D. LVPECL DC C ABLE HARACTERISTICS ...
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T YPICAL 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 85314BGI- -2.5V/3.3V LVPECL F IFFERENTIAL 155.52MH HASE OISE AT 12kHz to 20MHz ...
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P ARAMETER LVPECL V EE -1.8V ± -0.375V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy t sk( UTPUT KEW Phase Noise Plot Offset Frequency f 1 RMS Jitter ...
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CLK0 nQ0:nQ4 Q0: ROPAGATION ELAY IFFERENTIAL NPUT 80% Clock 20% Outputs UTPUT ISE ALL IME 85314BGI- -2.5V/3.3V LVPECL F IFFERENTIAL TO CLK1 nQ0:nQ4 Q0:Q4 P ...
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IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show PP CMR interface examples for the ...
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T 3.3V LVPECL O ERMINATION FOR The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- ...
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T 2.5V LVPECL O ERMINATION FOR Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to ter- minating 2V. For V = 2.5V, the 2.5V ...
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This section provides information on power dissipation and junction temperature for the ICS85314I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85314I-01 is the sum of the core power plus the power ...
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Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 6. F IGURE T o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage ...
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T 7A ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...
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ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 85314BGI- -2.5V/3.3V LVPECL F IFFERENTIAL TO TSSOP EAD 8A ACKAGE IMENSIONS ...
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ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MS-013, MO-119 85314BGI- -2.5V/3.3V LVPECL F IFFERENTIAL TO SOIC EAD 8B ACKAGE IMENSIONS ...
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ABLE RDERING NFORMATION ...
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