ICS8308AGILF IDT, Integrated Device Technology Inc, ICS8308AGILF Datasheet - Page 12

• Manufacturer Part Number: ICS8308AGILF
• Description: IC CLK BUFFER 1:8 350MHZ 24TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8308AGILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8308AGILF

ICS8308I Data Sheet
S
Figure 3 shows a schematic example of the ICS8308I. In this
example, the LVCMOS_CLK input is selected. The decoupling
Power On Sequence
There is no power on sequence requirement for the V
If the V
state at the outputs during initial condition when the V
and V
R
I
CLK I
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
ground.
LVCMOS C
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1k
ICS8308AGI REVISION C MARCH 23, 2011
NPUTS
CHEMATIC
ECOMMENDATIONS FOR
resistor can be tied from the CLK input to ground.
DD
NPUT
DDO
:
is off.
(U1,9)
is turned on before the V
VDD
ONTROL
C1
0.1u
NPUTS
E
VDD
XAMPLE
3.3V_LVCMOS
Ro ~ 7 Ohm
(U1,12)
resistor can be used.
P
INS
C2
0.1u
R11
VDD=3.3V
(U1,16)
43
U
Zo = 50 Ohm
NUSED
C3
0.1u
resistor can be tied from CLK to
(U1,20)
DD,
F
there will be unknown
I
IGURE
NPUT AND
1K
C4
0.1u
R9
(U1,24)
1K
R10
3. ICS8308I LVPECL B
1K
C5
0.1u
VDD
R12
O
UTPUT
DD
DDO
VDD
and V
is on
P
DDO.
INS
10
11
12
1
2
3
4
5
6
7
8
9
U1
12
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Q0
GND
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
VDD
GND
Q1
VDDO
ICS8308I
capacitors should be physically located near the power pin.
O
LVCMOS O
All unused LVCMOS output can be left floating. There should be
no trace attached.
UFFER
UTPUTS
S
CHEMATIC
:
VDDO
VDDO
VDDO
GND
GND
GND
UTPUTS
Q2
Q3
Q4
Q5
Q6
Q7
24
23
22
21
20
19
18
17
16
15
14
13
E
XAMPLE
VDD
R1
R8
43
43
Zo = 50 Ohm
Zo = 50 Ohm
2011 Integrated Device Technology, Inc.
3.3V LVCMOS/LVTTL
3.3V LVCMOS/LVTTL