ICS858012AKLF IDT, Integrated Device Technology Inc, ICS858012AKLF Datasheet

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ICS858012AKLF

Manufacturer Part Number
ICS858012AKLF
Description
IC FANOUT BUFFER 1-2 16-VFQFPN
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of ICS858012AKLF

Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVPECL
Frequency - Max
2GHz
Voltage - Supply
2.375 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-VFQFN
Frequency-max
2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
858012AKLF
B
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product
characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-
tions without notice.
858012AK
G
low output skew, making it suitable for use in demanding
applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated
differential input and V
families such as LVPECL, LVDS, LVHSTL and HCSL to be
easily interfaced to the input with minimal use of external
components. The ICS858012 is packaged in a small 3mm x
3mm 16-pin VFQFN package which makes it ideal for use in
space-constrained applications.
HiPerClockS™
ICS
LOCK
ENERAL
V
REF_AC
nIN
IN
V
T
D
The ICS858012 is a high speed 1-to-2 Differential-
to-2.5V, 3.3V LVPECL Fanout Buffer and is a
member of the
performance clock solutions from ICS. The
ICS858012 is optimized for high speed and very
IAGRAM
D
ESCRIPTION
REF
_
AC
pin allow other differential signal
HiPerClockS™
PRELIMINARY
family of high
Q0
nQ0
Q1
nQ1
1
F
• Two differential LVPECL outputs
• One differential LVPECL clock input
• IN, nIN pair can accept the following differential input
• Output frequency: 2GHz (typical)
• Output skew: <15ps (typical)
• Part-to-part skew: TBD
• Additive phase jitter, RMS: TBD
• Propagation delay: 350ps (typical)
• Operating voltage supply range:
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS5) and lead-free (RoHS 6)
P
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
V
packages
EATURES
IN
CC
= 2.375V to 3.63V, V
2.5V, 3.3V LVPECL F
A
L
SSIGNMENT
OW
3mm x 3mm x 0.95 package body
V
S
REF
KEW
nIN
_
V
IN
AC
T
16-Lead VFQFN
1
2
3
4
ICS858012
, 1-
16 15 14 13
5
K Package
EE
Top View
6
TO
= 0V
7
-2, D
8
12
11
10
9
ICS858012
Q0
nQ0
nQ1
Q1
IFFERENTIAL
ANOUT
REV. A OCTOBER 28, 2008
B
UFFER
-
TO
-

Related parts for ICS858012AKLF

ICS858012AKLF Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS858012 is a high speed 1-to-2 Differential- ICS to-2.5V, 3.3V LVPECL Fanout Buffer and is a HiPerClockS™ member of the HiPerClockS™ performance clock solutions from ICS. The ICS858012 is optimized for high speed and very ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Input Current, IN, nIN V Current Input Sink/Source, I REF_AC Operating Temperature Range, TA -40°C to +85°C ...

Page 4

0V; V ABLE HARACTERISTICS ...

Page 5

P ARAMETER LVPECL V EE -0.375V to -1.63V UTPUT OAD EST IRCUIT nQx PART 1 Qx nQy PART 2 Qy tsk(pp ART TO ART KEW nIN IN nQ0, ...

Page 6

LVPECL NPUT WITH UILT N The IN/nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V and V must meet the V SWING OH ments. Figures show ...

Page 7

LVPECL NPUT WITH UILT N The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V and V must meet the V SWING OH ments. Figures ...

Page 8

D I IFFERENTIAL NPUT WITH To prevent oscillation and to reduce noise recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 3. 3. IFFERENTIAL NPUT ...

Page 9

R U ECOMMENDATIONS FOR NUSED O : UTPUTS LVPECL O UTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or ...

Page 10

T 2.5V LVPECL O ERMINATION FOR Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminat- ing 50Ω 2V. For V = 2.5V, the 2.5V ...

Page 11

This section provides information on power dissipation and junction temperature for the ICS858012. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS858012 is the sum of the core power plus the power ...

Page 12

Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of ...

Page 13

ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS858012 is: 113 Pin compatible with SY58012U 858012AK PRELIMINARY L 2.5V, 3.3V ...

Page 14

ACKAGE UTLINE UFFIX FOR T Reference Document: JEDEC Publication 95, MO-220 858012AK PRELIMINARY L 2.5V, 3.3V LVPECL F VFQFN EAD ABLE ACKAGE IMENSIONS ...

Page 15

ABLE RDERING NFORMATION ...

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