ICS85301AKLFT IDT, Integrated Device Technology Inc, ICS85301AKLFT Datasheet - Page 10

• Manufacturer Part Number: ICS85301AKLFT
• Description: IC MUX 2:1 DIFF-LVPECL 16-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Multiplexerr

Specifications of ICS85301AKLFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VFQFN
• Frequency-max: 3GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85301AKLFT

R
I
PCLK/nPCLK I
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1k
from PCLK to ground.
T
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
IDT
RTT =
NPUTS
ERMINATION FOR
ECOMMENDATIONS FOR
ICS85301
2:1, DIFFERENTIAL-TO-LVPECL MULTIPLEXER
™
/ ICS
((V
:
F
™
FOUT
OH
IGURE
2:1, LVPECL MULTIPLEXER
+ V
OL
NPUT
3A. LVPECL O
) / (V
1
:
CC
3.3V LVPECL O
Z
Z
– 2)) – 2
o
o
= 50
= 50
U
NUSED
Z
o
50
UTPUT
I
NPUT
T
RTT
ERMINATION
UTPUT
50
resistor can be tied
P
V
CC
INS
FIN
- 2V
10
drive 50
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT
F
IGURE
transmission lines. Matched impedance techniques
3B. LVPECL O
Z
Z
o
o
= 50
= 50
ICS85301 REV. B DECEMBER 22, 2006
125
84
UTPUT
3.3V
125
84
T
ERMINATION
FIN