CY29972AXI Cypress Semiconductor Corp, CY29972AXI Datasheet - Page 2

• Manufacturer Part Number: CY29972AXI
• Description: IC CLK ZDB 12OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Spread Spectrum Clock Generator, Zero Delay Bufferr

Specifications of CY29972AXI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: Clock, Crystal
• Output: Clock
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.9 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 125MHz
• Maximum Input Frequency: 480 MHz
• Minimum Input Frequency: 200 MHz
• Output Frequency Range: 125 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.9 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2236; CY29972AXI

Document #: 38-07290 Rev. *C
Pin Description
Note:
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
35, 39, 47, 51
33,37, 45, 49
1, 15, 24, 30,
2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their
17, 22, 28,
5, 26, 27
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
42, 43
40, 41
19, 20
Pin
12
10
29
25
52
31
14
13
11
9
6
7
8
2
3
4
FB_SEL(2:0)
TCLK_SEL
SELA(1,0)
SELB(1,0)
SELC(1,0)
VCO_SEL
REF_SEL
[2]
INV_CLK
FB_OUT
MR#/OE
PLL_EN
QA(3:0)
QB(3:0)
QC(3:0)
SYNC
FB_IN
Name
T
T
S
X
V
S
V
V
X
CLK0
CLK1
DATA
DDC
OUT
CLK
DD
SS
IN
PWR
V
V
V
V
V
DDC
DDC
DDC
DDC
DDC
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Oscillator Input. Connect to a crystal.
Oscillator Output. Connect to a crystal.
External Reference/Test Clock Input.
External Reference/Test Clock Input.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 on page 3 for frequency selections.
Clock Outputs. See Table 2 on page 3 for frequency selections.
Feedback Clock Output. Connect to FB_IN for normal operation.
The divider ratio for this output is set by FB_SEL(0:2). See Table 1
on page 1. A bypass delay capacitor at this output will control Input
Reference/ Output Banks phase relationships.
Synchronous Pulse Output. This output is used for system
synchronization. The rising edge of the output pulse is in sync with
both the rising edges of QA (0:3) and QC(0:3) output clocks
regardless of the divider ratios selected.
Frequency Select Inputs. These inputs select the divider ratio at
QA(0:3) outputs. See Table 2.
Frequency Select Inputs. These inputs select the divider ratio at
QB(0:3) outputs. See Table 2.
Frequency Select Inputs. These inputs select the divider ratio at
QC(0:3) outputs. See Table 2.
Feedback Select Inputs. These inputs select the divide ratio at
FB_OUT output. See Table 1 on page 1.
VCO Divider Select Input. When set LOW, the VCO output is
divided by 2. When set HIGH, the divider is bypassed. See Table 1
on page 1.
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL Enable Input. When asserted HIGH, PLL is enabled; when
LOW, PLL is bypassed.
Reference Select Input. When HIGH, the crystal oscillator is
selected; when LOW, TCLK (0,1) is the reference clock.
TCLK Select Input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
Master Reset/Output Enable Input. When asserted LOW, resets
all of the internal flip-flops and also disables all of the outputs. When
pulled high, releases the internal flip-flops from reset and enables all
of the outputs.
Inverted Clock Input. When set HIGH, QC(2,3) outputs are
inverted. When set LOW, the inverter is bypassed.
Serial Clock Input. Clocks data at SDATA into the internal register.
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
3.3V power supply for output clock buffers.
3.3V power supply for PLL.
Common ground.
Description
CY29972
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