CY29972AXI Cypress Semiconductor Corp, CY29972AXI Datasheet - Page 3

• Manufacturer Part Number: CY29972AXI
• Description: IC CLK ZDB 12OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Spread Spectrum Clock Generator, Zero Delay Bufferr

Specifications of CY29972AXI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: Clock, Crystal
• Output: Clock
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.9 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 125MHz
• Maximum Input Frequency: 480 MHz
• Minimum Input Frequency: 200 MHz
• Output Frequency Range: 125 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.9 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2236; CY29972AXI

Document #: 38-07290 Rev. *C
Description
The CY29972 has an integrated PLL that provides low skew
and low jitter clock outputs for high-performance micropro-
cessors. Three independent banks of four outputs and an
independent PLL feedback output (FB_OUT) provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the V
run between 200 MHz and 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input (FB_IN) is connected to the feedback output
(FB_OUT). The internal V
reference clock set by FB_SEL(0:2) and VCO_SEL select
inputs (refer to Frequency Table). The V
divided to provide the required output frequencies. These
dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select
inputs (see Table 2 below). For situations were the V
to run at relatively low frequencies and hence might not be
stable, assert VCO_SEL low to divide the VCO frequency by
2. This will maintain the desired output relationships but will
provide an enhanced PLL lock range.
Table 2.
VCO_SEL
0
0
0
0
1
1
1
1
SELA1
0
0
1
1
0
0
1
1
CO
is running at multiples of the input
SELA0
0
1
0
1
0
1
0
1
CO
CO
VCO/12
VCO/16
VCO/24
VCO/12
VCO/8
VCO/4
VCO/6
VCO/8
frequency is then
QA
is configured to
CO
needs
SELB1
0
0
1
1
0
0
1
1
The CY29972 is also capable of providing inverted output
clocks. When INV_CLK is asserted HIGH, QC2 and QC3
output clocks are inverted. These clocks could be used as
feedback outputs to the CY29972 or a second PLL device to
generate early or late clocks for a specific design. This
inversion does not affect the output to output skew.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed “on the fly,” their output clock periods will:
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
1. contain short or “runt” clock periods. These are clock cycles
2. contain stretched clock periods. These are clock cycles in
SELB0
in which the cycle(s) are shorter in period than either the
old or new frequencies to which the cycles are being transi-
tioned.
which the cycle(s) are longer in period than either the old
or new frequencies to which the cycles are being transi-
tioned.
0
1
0
1
0
1
0
1
VCO/12
VCO/16
VCO/20
VCO/10
VCO/8
VCO/4
VCO/6
VCO/8
QB
SELC1
0
0
1
1
0
0
1
1
SELC0
0
1
0
1
0
1
0
1
CY29972
Page 3 of 8
VCO/12
VCO/16
VCO/4
VCO/8
VCO/2
VCO/4
VCO/6
VCO/8
QC
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