IDTCSP2510CPG IDT, Integrated Device Technology Inc, IDTCSP2510CPG Datasheet - Page 3

• Manufacturer Part Number: IDTCSP2510CPG
• Description: IC PLL CLK DRIVER 3.3V 24-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Driver, Zero Delay Bufferr

Specifications of IDTCSP2510CPG

• Pll: Yes with Bypass
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: No/No
• Frequency - Max: 140MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Frequency-max: 140MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CSP2510CPG

PIN DESCRIPTION
STATIC FUNCTION TABLE
IDTCSP2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
FBOUT
Y (0:9)
AGND
Name
FBIN
AV
GND
CLK
V
G
DD
DD
Terminal
H
H
H
G
L
L
2, 10, 14, 22 Power
3, 4, 5, 8, 9,
6, 7, 18, 19 Ground
15, 16, 17,
Inputs
20, 21
No.
24
13
11
12
23
1
running
CLK
Ground
Power
Type
H
H
L
L
O
O
I
I
I
Clock input. CLK provides the clock signal to be distributed by the CSP2510C clock driver. CLK is used to provide the reference signal
to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase
lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback
signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When
G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be
disabled to a logic-low state by de-asserting the G control input.
Analog power supply. AV
for test purposes. When AV
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
Ground
running
Y (0:9)
H
L
L
L
(AV
Outputs
DD
DD
= 0V)
DD
provides the power reference for the analog circuitry. In addition, AV
FBOUT
running
is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
H
H
L
L
3
DYNAMIC FUNCTION TABLE
H
H
G
X
L
L
Description
Inputs
running
running
CLK
H
H
L
0ºC TO 85ºC TEMPERATURE RANGE
phase with CLK
running in
Y (0:9)
DD
H
L
L
L
can be used to bypass the PLL
Outputs
(AV
phase with CLK
phase with CLK
running in
running in
FBOUT
DD
H
H
L
= 3.3V)