ICS342MP IDT, Integrated Device Technology Inc, ICS342MP Datasheet - Page 2

• Manufacturer Part Number: ICS342MP
• Description: IC VERSACLOCK SYNTHESIZER 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS342MP

• Pll: Yes
• Input: Clock, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 342MP

Pin Assignment
Pin Description
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20 .
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS342
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 2
ICS342
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
X 1 / I C L K
C L K 1
G N D
V D D
Number
Pin
1
2
3
4
5
6
7
8
8-pin (150 mil) SOIC
1
2
3
4
X1/ICLK
Name
PDTS
CLK1
CLK2
GND
VDD
SEL
Pin
X2
8
7
6
5
Output
Output
Power
Power
X 2
P D T S
S E L
C L K 2
Type
Input
Input
Pin
XO
XI
Connect this pin to a crystal or external clock input.
Connect to +3.3 V.
Connect to ground.
Clock output. Weak internal pull-down when tri-state.
Clock output. Weak internal pull-down when tri-state.
Select for frequency selection on CLK1 and CLK2. Internal pull-up resistor.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up
resistor.
Connect this pin to a crystal, or float for clock input.
Output Clock Selection Table
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
pF)*2. In this equation, C
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
SEL CLK1 (MHz) CLK2 (MHz)
0
1
Configurable
Configurable
Pin Description
User
User
Configurable
Configurable
L
= crystal load capacitance in pF.
User
User
EPROM CLOCK SYNTHESIZER
ICS342
Percentage
Configurable
Configurable
Spread
User
User
REV M 051310
L
-6