MPC9653AACR2/W IDT, Integrated Device Technology Inc, MPC9653AACR2/W Datasheet - Page 6

• Manufacturer Part Number: MPC9653AACR2/W
• Description: IC PLL CLK GEN 1:8 3.3V 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9653AACR2/W

• Pll: Yes with Bypass
• Input: LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:8 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9653A
3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
Programming the MPC9653A
to 125 MHz. Two different feedback divider configurations can
be used to achieve the desired frequency operation range. The
feedback divider (VCO_SEL) should be used to situate the
VCO in the frequency lock range between 200 and 500 MHz for
stable and optimal operation. Two operating frequency ranges
Table 7. MPC9653A Configurations (QFB connected to FB_IN)
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the V
for instance I/O jitter. The MPC9653A provides separate power
supplies for the output buffers (V
(V
is to isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the V
illustrates a typical power supply filter scheme. The MPC9653A
frequency and phase stability is most susceptible to noise with
spectral content in the 100 kHz to 20 MHz range. Therefore, the
filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is the DC
voltage drop across the series filter resistor R
sheet the I
pin) is typically 5 mA (10 mA maximum), assuming that a
minimum of 2.985 V must be maintained on the V
534
BYPASS
CCA_PLL
The MPC9653A supports output clock frequencies from 25
The MPC9653A is a mixed analog/digital product. Its analog
0
1
1
1
1
CCA_PLL
V
CC
CCA
) of the device. The purpose of this design technique
Figure 3. V
PLL_EN
power supply impacts the device characteristics,
current (the current sourced through the V
R
X
0
0
1
1
F
= 5–15 Ω
CC_PLL
R
F
CC_PLL
VCO_SEL
C
F
pin for the MPC9653A.
X
0
1
0
1
33...100 nF
Power Supply Filter
CC
C
F
10 nF
= 22 µF
) and the phase-locked loop
Test mode: PLL and divider bypass
Test mode: PLL bypass
Test mode: PLL bypass
PLL mode (high frequency range)
PLL mode (low frequency range)
V
V
F
CC_PLL
CC
. From the data
APPLICATIONS INFORMATION
Operation
MPC9653A
CC_PLL
Figure 3
CC_PLL
pin.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
6
are supported: 25 to 62.5 MHz and 50 to 125 MHz.
illustrates the configurations supported by the MPC9653A. PLL
zero-delay is supported if BYPASS = 1, PLL_EN = 1 and the
input frequency is within the specified PLL reference frequency
range.
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in
and the noise attenuation at 100 kHz is better than 42 dB.
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9653A has several
design features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
Using the MPC9653A in Zero-Delay Applications
MPC9653A. Designs using the MPC9653A as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9653A clock driver allows for its use as a zero-delay buffer.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the
device (the propagation delay through the device is virtually
eliminated). The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter), feedback
path delay and the output-to-output skew error relative to the
feedback output.
The minimum values for R
As the noise frequency crosses the series resonant point of
Nested clock trees are typical applications for the
f
f
Q0–7
Q0–7
f
f
f
Q0–7
Q0–7
Q0–7
Ratio
= f
= f
Figure
= f
= f
= f
REF
REF
REF
REF
REF
÷ 4
÷ 8
3, the filter cut-off frequency is around 4 kHz
Output Range (f
25 to 62.5 MHz
50 to 125 MHz
0 – 200 MHz
0 – 50 MHz
0 – 25 MHz
Frequency
F
and the filter capacitor C
Q0–7
)
f
f
VCO
VCO
VCO
= f
= f
Table 7
n/a
n/a
n/a
REF
REF
NETCOM
F
are
MPC9653A
⋅ 4
⋅ 8