MPC9351ACR2 IDT, Integrated Device Technology Inc, MPC9351ACR2 Datasheet

MPC9351ACR2

Manufacturer Part Number

MPC9351ACR2

Description

IC PLL CLOCK DRIVER LV 32-LQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheet

1.MPC9351ACR2.pdf (12 pages)

Specifications of MPC9351ACR2

Pll

Yes with Bypass

Input

LVCMOS, LVPECL

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

2:9

Differential - Input:output

Yes/No

Frequency - Max

200MHz

Divider/multiplier

Yes/No

Voltage - Supply

2.375 V ~ 3.465 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

32-LQFP

Frequency-max

200MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MPC9351ACR2

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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IDT™ Low Voltage PLL Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

Low Voltage PLL Clock Driver

Freescale Semiconductor

Technical Data

Low Voltage PLL Clock Driver

targeted for high performance clock distribution systems. With output

frequencies of up to 200 MHz and a maximum output skew of 150 ps, the

MPC9351 is an ideal solution for the most demanding clock tree designs. The

device offers 9 low-skew clock outputs, each is configurable to support the

clocking needs of the various high-performance microprocessors including the

PowerQUICC II integrated communication microprocessor. The extended

temperature range of the MPC9351 supports telecommunication and networking

requirements.The device employs a fully differential PLL design to minimize

cycle-to-cycle and long-term jitter.

Features

•

Functional Description

of the MPC9351 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The

reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to

match the VCO frequency range. With available output dividers of divide-by-2, divide-by-4 and divide-by-8, the internal VCO of

the MPC9351 is running at either 2x, 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs

is either the one-half, one-fourth or one-eighth of the selected VCO frequency and can be configured for each output bank using

the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output-to-input frequency ratios are 4:1, 2:1, 1:1, 1:2

and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input

(TCLK). The MPC9351 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test

mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended

for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification

does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes

the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase

locked loop, also enabling the PLL to recover to normal operation. The MPC9351 is fully 2.5 V and 3.3 V compatible and requires

no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals, while the outputs provide

LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission

lines, each of the MPC9351 outputs can drive one or two traces giving the device an effective fanout of 1:18. The device is pack-

aged in a 7x7 mm

Application Information

zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between

the outputs and the reference signal.

The MPC9351 is a 2.5 V and 3.3 V compatible, PLL based clock generator

The MPC9351 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation

The fully integrated PLL of the MPC9351 allows the low-skew outputs to lock onto a clock input and distribute it with essentially

9 outputs LVCMOS PLL clock generator

25 – 200 MHz output frequency range

Fully integrated PLL

2.5 V and 3.3 V compatible

Compatible to various microprocessors such as PowerQuicc II

Supports networking, telecommunications and computer applications

Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

LVPECL and LVCMOS compatible inputs

External feedback enables zero-delay configurations

Output enable/disable and static test mode (PLL enable/disable)

Low skew characteristics: maximum 150 ps output-to-output

Cycle-to-cycle jitter max. 22 ps RMS

32-lead LQFP package

32-lead Pb-free Package Available

Ambient Temperature Range -40°C to +85°C

32-lead LQFP package.

32-LEAD LQFP PACKAGE

CLOCK GENERATOR

2.5 V AND 3.3 V PLL

Pb-FREE PACKAGE

LOW VOLTAGE

CASE 873A-03

FA SUFFIX

AC SUFFIX

DATA SHEET

Rev. 5, 1/2005

MPC9351

Related parts for MPC9351ACR2

MPC9351ACR2 Summary of contents

Page 1

Freescale Semiconductor Technical Data Low Voltage PLL Clock Driver Low Voltage PLL Clock Driver The MPC9351 is a 2.5 V and 3.3 V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up ...

Page 2

MPC9351 Low Voltage PLL Clock Driver (Pullup) PCLK PCLK (Pulldown) TCLK (Pulldown) REF_SEL (Pulldown) EXT_FB (Pullup) PLL_EN (Pulldown) FSELA (Pulldown) FSELB (Pulldown) FSELC (Pulldown) FSELD (Pulldown) OE The MPC9351 requires an external RC filter for the analog power supply pin ...

Page 3

MPC9351 Low Voltage PLL Clock Driver Table 1. Pin Descriptions Number Name PCLK, PCLK Input TCLK Input EXT_FB Input REF_SEL Input FSELA Input FSELB Input FSELC Input FSELD Input OE Input QA Output QB Output QC0, QC1 Output QD0 – ...

Page 4

MPC9351 Low Voltage PLL Clock Driver Table 5. DC Characteristics (V CC Symbol Characteristics V Input High Voltage IH V Input Low Voltage IL V Peak-to-Peak Input Voltage PP (1) V Common Mode Range CMR V Output High Voltage OH ...

Page 5

MPC9351 Low Voltage PLL Clock Driver Table 7. DC Characteristics (V CC Symbol Characteristics V Input High Voltage IH V Input Low Voltage IL V Peak-to-Peak Input Voltage PP (1) V Common Mode Range CMR V Output High Voltage OH ...

Page 6

MPC9351 Low Voltage PLL Clock Driver Programming the MPC9351 The MPC9351 clock driver outputs can be configured into several divider modes; in addition, the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. ...

Page 7

MPC9351 Low Voltage PLL Clock Driver Calculation of Part-to-Part Skew The MPC9351 zero-delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC9351 ...

Page 8

MPC9351 Low Voltage PLL Clock Driver designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor ( current (the current ...

Page 9

MPC9351 Low Voltage PLL Clock Driver 3.0 OutA OutB 2 3.8956 3.9386 D 2.0 In 1.5 1.0 0 Time (ns) Figure 9. Single versus Dual Waveforms Pulse Generator Z = 50Ω ...

Page 10

MPC9351 Low Voltage PLL Clock Driver PCLK V CMR PCLK Ext_FB t (∅) Figure 13. Propagation Delay (t Test Reference The time from the PLL controlled edge to the non-controlled edge, divided by ...

Page 11

MPC9351 Low Voltage PLL Clock Driver D1/2 PIN 1 INDEX E1 D/2 4X 0. 28X SEATING PLANE (S) A1 DETAIL AD IDT™ Low ...

Page 12

MPC92459 MPC9351 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Voltage PLL Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters ...

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