MPC93R51ACR2 IDT, Integrated Device Technology Inc, MPC93R51ACR2 Datasheet - Page 7

• Manufacturer Part Number: MPC93R51ACR2
• Description: IC PLL CLK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC93R51ACR2

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: Yes/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93R51
Low Voltage PLL Clock Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Calculation of Part-to-Part Skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC93R51 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter.
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from
Table 8. Confidence Factor CF
layout and can be used to fine-tune the effective delay
through each device. In the following example
an
resulting in a worst case timing uncertainty from input to any
output of –251 ps to 351 ps relative to TCLK (V
f
t
t
shown in the AC characteristic table for V
RMS). I/O jitter is frequency dependent with a maximum at
VCO
SK(PP)
SK(PP)
The MPC93R51 zero delay buffer supports applications
This maximum timing uncertainty consists of 4
Due to the statistical nature of I/O jitter, a RMS value (1 σ)
The feedback trace delay is determined by the board
Above equation uses the maximum I/O jitter number
I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
Figure 4. MPC93R51 Max. Device-to-Device Skew
CF
Any Q
Any Q
TCLK
= 400 MHz):
QFB
QFB
t
Max. skew
SK(PP)
= [-50ps...150ps] + [-150ps...150ps] +
= [-251ps...351ps] + t
Common
Device 1
Device 1
Device 2
Device2
[(17ps · –3)...(17ps ·3)] + t
Probability of clock edge within the distribution
= t
(∅)
+ t
SK(O)
t
JIT(∅)
—t
Table
+t
+ t
(∅)
SK(O)
PD, LINE(FB)
PD, LINE(FB)
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
8.
+t
(∅)
PD, LINE(FB)
t
JIT(∅)
t
SK(PP)
CC
+ t
t
+t
JIT(∅)
PD,LINE(FB)
= 3.3 V (17 ps
SK(O)
CC
calculation,
= 3.3 V and
· CF
7
the lowest VCO frequency (200 MHz for the MPC93R51).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in
I/O jitter number at the specific VCO frequency, resulting in
tighter timing limits in zero-delay mode and for part-to-part
skew t
Power Supply Filtering
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Noise on the V
characteristics, for instance, I/O jitter. The MPC93R51
provides separate power supplies for the output buffers (V
and the phase-locked loop (V
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the V
pin for the MPC93R51.
The MPC93R51 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range; therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop across the series filter
resistor R
sourced through the V
maximum), assuming that a minimum of 3.0 V must be
maintained on the V
Figure 6
voltage drop criteria.
The MPC93R51 is a mixed analog/digital product. Its
Figure 6
Figure 5. Max. I/O Jitter (RMS) Versus Frequency
30
25
20
15
10
5
0
SK(PP)
75
must have a resistance of 5-15 Ω to meet the
F
. From the data sheet, the I
illustrates a typical power supply filter scheme.
.
225
CCA
Max. I/O Jitter versus frequency
Figure 5
250
(PLL) power supply impacts the device
CCA
CCA
for V
pin. The resistor R
275
can be used to derive a smaller
pin) is typically 3 mA (5 mA
CC
CCA
300
= 3.3 V
) of the device. The purpose
325
CCA
VCO frequency [MHz]
current (the current
350
F
shown in
375
MPC93R51
400
NETCOM
CCA
CC
MPC93R51
7
)