MPC9772AER2 IDT, Integrated Device Technology Inc, MPC9772AER2 Datasheet
MPC9772AER2
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MPC9772AER2 Summary of contents
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LVCMOS PLL CLOCK GENERATOR 3.3 V 1:12 LVCMOS PLL Clock Generator The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR All input resistors have a value of 25kΩ XTAL_IN XTAL 1 XTAL_OUT CCLK0 0 1 CCLK1 CCLK_SEL V CC REF_SEL FB_IN VCO_SEL PLL_EN V CC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] V ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configuration Pin I/O CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock XTAL_IN, XTAL_OUT FB_IN Input LVCMOS PLL feedback signal input, connect to an QFB CCLK_SEL ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 2. Function Table (Configuration Controls) Control Default REF_SEL 1 Selects CCLKx as the PLL reference clock CCLK_SEL 1 Selects CCLK0 VCO_SEL 1 Selects VCO÷2. The VCO frequency is scaled by a factor ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 5. Output Divider Bank C (N VCO_SEL Table 6. Output Divider PLL Feedback (M) VCO_SEL FSEL_FB2 ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 9. DC Characteristics (V CC Symbol Characteristics V PLL Supply Voltage CC_PLL V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage OL ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 10. AC Characteristics (V Symbol Characteristics t Propagation Delay (static phase offset) (∅) CCLK to FB_IN 6.25 MHz < f 65.0 MHz < =50 MHz and feedback=÷8 REF (8) t ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR MPC9772 Configurations Configuring the MPC9772 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ M ÷ ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR CCLK0 QA[3: 33.3 MHz CCLK1 ref CCLK_SEL QB[3:0] 1 VCO_SEL FB_IN FSEL_A[1:0] 11 QC[3:0] 00 FSEL_B[1:0] 00 FSEL_C[1:0] 101 FSEL_FB[2:0] MPC9772 33.3 MHz (Feedback) MPC9772 example configuration (feedback of QFB = ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR f VCO QA QC QSYNC QA QC QSYNC QC(÷2) QA(÷6) QSYNC QA(÷4) QC(÷6) QSYNC QC(÷2) QA(÷8) QSYNC QA(÷6) QC(÷8) QSYNC QA(÷12) QC(÷2) QSYNC IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 1:1 ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Power Supply Filtering The MPC9772 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Due to the statistical nature of I/O jitter a RMS value (1 σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Table 12. Confidence Factor ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR MPC9772 Output Buffer = 36 Ω 14Ω In MPC9772 Output = 36 Ω R Buffer S 14Ω Ω Figure 12. Single versus Dual Transmission Lines The ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output-to-Output Skew ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 4X 0.20 (0.008 -H- -T- SEATING PLANE 0.05 (0.002 VIEW AA IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK ...
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MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...