MPC9658AC IDT, Integrated Device Technology Inc, MPC9658AC Datasheet - Page 8

• Manufacturer Part Number: MPC9658AC
• Description: IC PLL CLK GEN 1:10 3.3V 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9658AC

• Pll: Yes with Bypass
• Input: LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR
MPC9658
3.3V 1:10 LVCMOS PLL CLOCK GENERATOR
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9658 output buffer
is more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9658. The output waveform
in
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 7
In
In
At the load end the voltage will double, due to the near
The waveform plots in
Figure 6. Single versus Dual Transmission Lines
MPC958
MPC958
Output
Output
Buffer
14 Ω
Buffe
14 Ω
shows a step in the waveform. This step is caused
V
Z
R
R
V
0
L
S
0
L
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18+14+25)
= 1.31 V
S
(Z
R
R
R
S
S
S
0
= 36 Ω
= 36 Ω
= 36 Ω
Figure 7
÷ (R
Generator
Z = 50 Ω
Pulse
S
+R
show the simulation
0
Z
Z
Z
O
O
O
+Z
= 50 Ω
= 50 Ω
= 50 Ω
0
Figure 9. PCLK MPC9658 AC Test Reference
))
V
TT
Z
O
= 50 Ω
R
T
OutA
OutB0
OutB1
= 50 Ω
8
MPC9658 DUT
cause any false clock triggering. However, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in
terminating resistors are reduced such that, when the
parallel combination is added to the output buffer impedance,
the line impedance is perfectly matched.
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 8. Optimized Dual Line Termination
Figure 7. Single versus Dual Waveforms
MPC958
Figure 8
Output
Buffe
14 Ω
14 Ω + 22 Ω || 22Ω = 50 Ω || 50 Ω
t
D
2
= 3.8956
OutA
In
Z
4
should be used. In this case, the series
O
= 50 Ω
25 Ω = 25 Ω
R
R
S
S
= 22 Ω
= 22 Ω
6
R
MPC9658 REV 6 SEPTEMBER 29, 2006
T
Time (ns)
= 50 Ω
t
D
= 3.9386
OutB
8
V
Z
Z
TT
O
O
= 50 Ω
= 50 Ω
10
12
14