ICS951413CGLF IDT, Integrated Device Technology Inc, ICS951413CGLF Datasheet - Page 2

• Manufacturer Part Number: ICS951413CGLF
• Description: IC SYSTEM CLOCK CHIP P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS951413CGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 951413CGLF

Pin Description
0929D—10/30/06
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
Integrated
Circuit
Systems, Inc.
X1
X2
VDD48
USB_48MHz
GND
VTT_PWRGD#/PD
SCLK
SDATA
**FS_C
**CLKREQA#
**CLKREQB#
SRCCLKT7
SRCCLKC7
VDDSRC
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
PIN NAME
TYPE
PWR Power pin for the 48MHz output.3.3V
PWR Ground pin.
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the SRC outputs
PWR Ground pin for the SRC outputs
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the SRC outputs
OUT Crystal output, Nominally 14.318MHz
OUT 48.00MHz USB clock
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential ATIGCLK clock pair.
OUT Complementary clock of differential ATIGCLK clock pair.
PIN
I/O
IN
IN
IN
IN
IN
IN
Crystal input, Nominally 14.318MHz.
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put
the device into a low power state. The internal clocks, PLLs and the crystal
oscillator are stopped.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Frequency select latch input pin
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
2
DESCRIPTION
ICS951413