MPC9772FA IDT, Integrated Device Technology Inc, MPC9772FA Datasheet - Page 4

• Manufacturer Part Number: MPC9772FA
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9772FA

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: No/No
• Frequency - Max: 240MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 240MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
Table 2. Function Table (Configuration Controls)
REF_SEL
CCLK_SEL
VCO_SEL
PLL_EN
INV_CLK
MR/OE
Table 3. Output Divider Bank A (N
Table 4. Output Divider Bank B (N
Table 5. Output Divider Bank C (N
VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency
Control
ratios. See
VCO_SEL
VCO_SEL
VCO_SEL
Default
Table 3
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
Selects CCLKx as the PLL reference clock
Selects CCLK0
Selects VCO÷2. The VCO frequency is scaled by a factor of 2 (low VCO
frequency range).
Test mode with the PLL bypassed. The reference clock is substituted for the
internal VCO output. MPC9772 is fully static and no minimum frequency
limit applies. All PLL related AC characteristics are not applicable.
QC2 and QC3 are in phase with QC0 and QC1
Outputs disabled (high-impedance state) and device is reset. During
reset/output disable the PLL feedback loop is open and the internal VCO
is tied to its lowest frequency. The MPC9772 requires reset after any loss
of PLL lock. Loss of PLL lock may occur when the external feedback path
is interrupted. The length of the reset pulse should be greater than one
reference clock cycle (CCLKx). The device is reset by the internal power-
on reset (POR) circuitry during power-up.
to
Table 6
and the
A
B
C
)
)
)
Applications Information
FSEL_A1
FSEL_B1
FSEL_C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
for supported frequency ranges and output to input frequency ratios.
4
FSEL_A0
FSEL_B0
FSEL_C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Selects the crystal oscillator as the PLL
reference clock
Selects CCLK1
Selects VCO÷1. (high VCO frequency range)
Normal operation mode with PLL enabled.
QC2 and QC3 are inverted (180° phase shift)
with respect to QC0 and QC1
Outputs enabled (active)
MPC9772 REV 6 FEBRUARY 7, 2007
1
VCO÷12
VCO÷16
VCO÷24
VCO÷12
VCO÷12
VCO÷16
VCO÷20
VCO÷10
VCO÷12
VCO÷16
QA[0:3]
QB[0:3]
QC[0:3]
VCO÷8
VCO÷4
VCO÷6
VCO÷8
VCO÷8
VCO÷4
VCO÷6
VCO÷8
VCO÷4
VCO÷8
VCO÷2