IDT8737-11PGGI IDT, Integrated Device Technology Inc, IDT8737-11PGGI Datasheet - Page 3

• Manufacturer Part Number: IDT8737-11PGGI
• Description: IC CLK GEN DIFF-LVPECL 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of IDT8737-11PGGI

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8737-11PGGI

CONTROL INPUT FUNCTION TABLE
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
CLOCK INPUT FUNCTION TABLE
NOTES:
1. H = HIGH
2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.
IDT8737-11
LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL
L = LOW
CLK or PCLK
MR
xCLK, xPCLK
1
0
0
0
0
xQA0, xQA1,
xQB0, xQB1
Biased
Biased
CLK, PCLK
QA0, QA1,
QB0, QB1
CLK_EN
0
1
0
1
(2)
(2)
CLK_EN
Inputs
X
0
0
1
1
xCLK or xPCLK
Biased
Biased
Inputs
1
0
1
0
(2)
(2)
CLK_SEL
X
0
1
0
1
Disabled
QAx
H
H
H
L
L
L
Selected Source
PCLK, xPCLK
PCLK, xPCLK
CLK, xCLK
CLK, xCLK
xQAx
X
H
H
H
L
L
L
CLK_EN Timing Diagram
Outputs
(1)
(1,2)
QBx
H
H
H
L
L
L
Disabled; LOW
Disabled; LOW
3
QA0, QA1
≈
≈
≈
Enabled
Enabled
LOW
xQBx
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
H
H
H
L
L
L
Disabled; HIGH
Disabled; HIGH
xQA0, xQA1
Enabled
Enabled
HIGH
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Input to Output Mode
Differential to Differential
Differential to Differential
Enabled
Outputs
Disabled; LOW
Disabled; LOW
QB0, QB1
Enabled
Enabled
LOW
Disabled; HIGH
Disabled; HIGH
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
xQB0, xQB1
Polarity
Inverting
Inverting
Enabled
Enabled
HIGH