MPC961CAC IDT, Integrated Device Technology Inc, MPC961CAC Datasheet - Page 4

• Manufacturer Part Number: MPC961CAC
• Description: IC BUFFER ZD 1:18 PLL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC961CAC

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:17
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC961C Data Sheet
Table 6. DC Characteristics (V
Table 7. AC Characteristics (V
MPC961C REVISION 5 AUGUST 17, 2009
1. The MPC961C is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. See
3. See
Symbol
Symbol
t
f
t
t
t
JIT(PER)
REFDC
PLZ
JIT(CC)
t
Z
PZL
t
I
f
DC
JIT(∅)
f
V
C
f
f
V
transmission line to a termination voltage of V
t
V
t
sk(O)
t
V
C
CCA
I
MAX
t
MAX
V
REF
REF
OUT
I
lock
r
r
CC
(∅)
OH
IN
, t
, t
OL
PD
TT
IH
IN
IL
,
,
O
HZ
LZ
f
f
APPLICATIONS INFORMATION
APPLICATIONS INFORMATION
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
Input Frequency
Maximum Output Frequency
Reference Input Duty Cycle
TCLK Input Rise/Fall Time
Propagation Delay
(static phase offset)
Output-to-Output Skew
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
Input Frequency
Maximum Output Frequency
Characteristics
Characteristics
CC
CC
(2)
= 2.5 V ± 5%, T
= 2.5 V ± 5%, T
for part-to-part skew calculation.
for calculation for other confidence factors than 1 σ.
TT
CCLK to FB_IN
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
. Alternatively, the device drives up two 50 Ω series terminated transmission lines.
RMS (1σ)
RMS (1σ)
RMS (1σ)
A
A
= –40° to 85°C)
= –40° to 85°C)
(3)
–0.3
Min
1.7
1.8
TT
.
Min
100
100
–80
100
100
0.1
50
50
25
40
45
50
50
(1)
V
4
CC
Typ
4.0
8.0
2.0
18
÷ 2
Typ
7.0
90
50
50
V
CC
±120
Max
0.7
0.6
5.0
26
10
+ 0.3
Max
200
100
200
100
120
150
200
100
200
100
3.0
1.0
75
60
55
10
10
15
10
15
10
Unit
mA
mA
µA
pF
pF
V
V
V
V
Ω
V
LVCMOS
LVCMOS
I
I
Per Output
V
All V
OH
OL
CCA
MHz
MHz
MHz
MHz
Unit
ms
ns
ps
ps
ns
ns
ns
ps
ps
ns
%
%
= 15 mA
= –15 mA
CC
©2009 Integrated Device Technology, Inc.
LOW VOLTAGE ZERO DELAY BUFFER
Pin
Pins
Condition
0.7 to 1.7 V
PLL locked
0.6 to 1.8 V
(1)
Condition
(1)