MPC9893AE IDT, Integrated Device Technology Inc, MPC9893AE Datasheet

MPC9893AE

Manufacturer Part Number

MPC9893AE

Description

IC PLL CLK GEN 1:12 3.3V 48-LQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheet

1.MPC9893AER2.pdf (13 pages)

Specifications of MPC9893AE

Pll

Yes with Bypass

Input

LVCMOS

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

2:12

Differential - Input:output

No/No

Frequency - Max

200MHz

Divider/multiplier

Yes/Yes

Voltage - Supply

2.375 V ~ 3.465 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-LQFP

Frequency-max

200MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Price

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Part Number:

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Download datasheet (357Kb)

3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

switch and generator specifically designed for redundant clock distribution systems. The

device receives two LVCMOS clock signals and generates 12 phase aligned output

clocks. The MPC9893 is able to detect a failing reference clock signal and to dynamically

switch to a redundant clock signal. The switch from the failing clock to the redundant clock

occurs without interruption of the output clock signal (output clock slews to alignment). The

phase bump typically caused by a clock failure is eliminated.

configurable to support the different clock frequencies.

networking requirements. The device employs a fully differential PLL design to minimize

jitter.

Features

•

Functional Description

generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two, three, four or eight.

The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same frequency than bank A or at half

of the bank A frequency. Therefore, bank B outputs additionally support the frequency multiplication of the input reference clock by 3÷2

and 1÷2. Bank A and bank B outputs are phase-aligned

also phase-aligned

monitors both clock inputs and indicates a clock failure individually for each clock input. When a false clock signal is detected, the

MPC9893 switches to the redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the

outputs. Both clock inputs are interchangeable, also supporting the switch to a failed clock that was restored. The MPC9893 also provides

a manual mode that allows for user-controlled clock switches.

is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can be disabled (high-im-

pedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893. On power-up this reset function

needs to be applied for correct operation of the circuitry. Please see the application section for power-on sequence recommendations.

1. At coincident rising edges.

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

The MPC9893 is a 2.5 V and 3.3 V compatible, PLL based intelligent dynamic clock

The device offers 12 low skew clock outputs organized into two output banks, each

The extended temperature range of the MPC9893 supports telecommunication and

The MPC9893 is a 3.3 V or 2.5 V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated PLL to

The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the MPC9893

The device is packaged in a 7x7 mm

12-output LVCMOS PLL clock generator

2.5 V and 3.3 V compatible

IDCS - on-chip intelligent dynamic clock switch

Automatically detects clock failure

Smooth output phase transition during clock failover switch

7.5 – 200 MHz output frequency range

LVCMOS compatible inputs and outputs

External feedback enables zero-delay configurations

Supports networking, telecommunications and computer applications

Output enable/disable and static test mode (PLL bypass)

Low skew characteristics: maximum 50 ps output-to-output (within bank)

48-lead LQFP package

48-lead Pb-free package available

Ambient operating temperature range of -40 to 85°C

(1)

to the selected input reference clock, providing virtually zero-delay capability. The integrated IDCS continuously

48-lead LQFP package.

(1)

. Due to the external PLL feedback, the clock signals of both output banks are

2.5 V AND 3.3 V IDCS AND

PLL CLOCK GENERATOR

48-LEAD LQFP PACKAGE

MPC9893

Pb-FREE PACKAGE

MPC9893

LOW VOLTAGE

CASE 932-03

FA SUFFIX

AE SUFFIX

SCALE 2:1

REV. 7 MARCH 3, 2008

MPC9893

Related parts for MPC9893AE

MPC9893AE Summary of contents

Page 1

LVCMOS PLL CLOCK GENERATOR The MPC9893 is a 2.5 V and 3.3 V compatible, PLL based intelligent dynamic clock switch and generator specifically designed for redundant clock distribution systems. The device receives two LVCMOS clock signals and generates ...

Page 2

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR CLK0 (Pulldown) CLK1 (Pulldown) FB (Pulldown) REF_SEL (Pulldown) MAN/A (Pullup) ALARM_RST (Pullup) PLL_EN (Pulldown) FSEL[0:3] (Pulldown) (Pulldown) OE/MR GND QA0 QA1 V GND QA2 QA3 V GND QA4 QA5 V IDT™ / ICS™ ...

Page 3

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configurations Number Name CLK0, CLK1 Input FB Input REF_SEL Input MAN/A Input ALARM_RST Input PLL_EN Input FSEL[0:3] Input OE/MR Input QA[0:5] Output QB[0:5] Output QFB Output ALARM0 Output ALARM1 Output ...

Page 4

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 3. Clock Frequency Configuration Name FSEL0 FSEL1 FSEL2 M82 M42 M32 ...

Page 5

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 6. DC Characteristics (V CC Symbol Characteristics V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH V Output Low Voltage OL Z Output Impedance OUT I ...

Page 6

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Table 8. AC Characteristics (V CC Symbol Characteristics f Input Frequency ref FSEL=000x f Maximum Output Frequency MAX f Reference Input Duty Cycle refDC CLK0, 1 Input Rise/Fall Time r ...

Page 7

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Definitions IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors both primary and secondary clock signals. Upon a failure of the primary clock signal, the IDCS switches to a valid secondary clock signal and ...

Page 8

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR R = 5–15Ω 33...100 nF Figure 3. V Power Supply Filter CC_PLL The minimum values for R and the filter capacitor C F defined ...

Page 9

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR The I/O (Phase) jitter of the MPC9893 depends on the internal VCO frequency and the PLL feedback divider configuration. A high internal VCO frequency and a low PLL feedback divider result in lower ...

Page 10

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR The waveform plots in Figure 9 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9893 output buffer is more ...

Page 11

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 12. Output-to-Output Skew ...

Page 12

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 4X 0.200 AB T 0.200 AC T BASE METAL ...

Page 13

MPC9893 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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