MPC9992AC IDT, Integrated Device Technology Inc, MPC9992AC Datasheet

MPC9992AC

Manufacturer Part Number

MPC9992AC

Description

IC PLL CLK GEN ECL/PECL 32-LQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheet

1.MPC9992ACR2.pdf (12 pages)

Specifications of MPC9992AC

Pll

Yes with Bypass

Input

PECL, Crystal

Output

PECL

Number Of Circuits

Ratio - Input:output

2:7

Differential - Input:output

Yes/Yes

Frequency - Max

400MHz

Divider/multiplier

Yes/No

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

32-LQFP

Frequency-max

400MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MPC9992AC

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MPC9992ACR2

Manufacturer:

IDT

Quantity:

1 130

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MPC9992ACR2

Manufacturer:

SAM

Quantity:

3 181

Company:

BOSTOCK HK LIMITED

Part Number:

MPC9992ACR2

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

3.3 V Differential ECL/PECL PLL

Clock Generator

Freescale Semiconductor

Technical Data

3.3 V Differential ECL/PECL PLL

Clock Generator

SiGe technology and a fully differential design ensures optimum skew and PLL

jitter performance. The performance of the MPC9992 makes the device ideal for

workstation, mainframe computer and telecommunication applications. With

output frequencies up to 400 MHz and output skews less than 100 ps the device

meets the needs of the most demanding clock applications. The MPC9992 offers

a differential PECL input and a crystal oscillator interface. All control signals are

LVCMOS compatible.

Features

•

Functional Description

quency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency

range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input

relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback fre-

quency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input ref-

erence frequency range.

erator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between

output frequencies.

nal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input

reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock

frequency specification and all other PLL characteristics do not apply.

Assertion of the reset signal forces all outputs to the logic low state.

PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels

with the capability to drive terminated 50 Ω transmission lines.

The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using

The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock fre-

The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC gen-

The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock sig-

The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted.

The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is

The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package.

7 differential outputs, PLL based clock generator

SiGe technology supports minimum output skew (max. 100 ps)

Supports up to two generated output clock frequencies with a maximum clock

frequency up to 400 MHz

Selectable crystal oscillator interface and PECL compatible clock input

SYNC pulse generation

PECL compatible differential clock inputs and outputs

Single 3.3 V (PECL) supply

Ambient temperature range 0°C to +70°C

Standard 32 lead LQFP package

Pin and function compatible to the MPC992

32-lead Pb-free Package Available

32-LEAD LQFP PACKAGE

CLOCK GENERATOR

3.3 V DIFFERENTIAL

Pb-FREE PACKAGE

MPC9992

CASE 873A-04

ECL/PECL

FA SUFFIX

AC SUFFIX

DATA SHEET

Rev 5, 06/2005

MPC9992

Related parts for MPC9992AC

MPC9992AC Summary of contents

Page 1

Freescale Semiconductor Technical Data 3.3 V Differential ECL/PECL PLL 3.3 V Differential ECL/PECL PLL Clock Generator Clock Generator The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum ...

Page 2

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator All input resistors have a value of 50kΩ XTAL_IN XTAL XTAL_OUT PCLK PCLK V REF_SEL V CC VCO_SEL PLL_EN V CC FSEL[1:0] MR/STOP MR/STOP MPC9992 IDT™ 3.3 V Differential ECL/PECL ...

Page 3

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Table 1. MPC9992 PLL Configurations VCO_SEL FSEL_0 FSEL_1 ...

Page 4

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Table 4. Absolute Maximum Ratings Symbol Characteristics V Supply Voltage Input Voltage Output Voltage OUT I DC Input Current Output Current OUT T ...

Page 5

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Table 6. DC Characteristics (V CC Symbol Characteristics Differential PECL Clock Inputs (PCLK, PCLK Differential Input Voltage PP V Differential Cross Point Voltage CMR (4) I Input Current IN LVCMOS ...

Page 6

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Table 7. AC Characteristics (V CC Symbol Characteristics f Input Reference Frequency ref Input Reference Frequency in PLL Bypass Mode f Crystal Interface Frequency Range XTAL f VCO Frequency Range VCO f ...

Page 7

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator SYNC Output Description The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system ...

Page 8

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Power Supply Filtering The MPC9992 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise ...

Page 9

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 873A-04 ISSUE ...

Page 10

MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator MPC9992 IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE Advanced ...

Page 11

Page 12

MPC92459 MPC9992 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3 V Differential ECL/PECL PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 ...

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