IDT5T2010BBI IDT, Integrated Device Technology Inc, IDT5T2010BBI Datasheet - Page 16
IDT5T2010BBI
Manufacturer Part Number
IDT5T2010BBI
Description
IC CLK DVR ZD PLL 2.5V 144-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
TeraClock™r
Type
PLL Clock Driverr
Datasheet
1.IDT5T2010NLGI8.pdf
(24 pages)
Specifications of IDT5T2010BBI
Pll
Yes with Bypass
Input
eHSTL, HSTL, LVPECL, LVTTL
Output
eHSTL, HSTL, LVTTL
Number Of Circuits
1
Ratio - Input:output
2:10
Differential - Input:output
Yes/No
Frequency - Max
250MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-BGA
Frequency-max
250MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
5T2010BBI
Available stocks
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Quantity
Price
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NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. t
3. The measurement is made at V
4. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
5. t
6. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken from V
7. t
8. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
9. t
10. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and FS = HIGH.
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.
12. For HSTL/eHSTL outputs only.
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
FB. For TxS/RxS = LOW, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay, FB input divider set to divide-
by-one, and FS = HIGH.
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified
limits.
SK
SK
ODCV
L
, t
t
t
Symbol
L
L
(
(
t
t
t
(
(
t
JIT
B
PR
L
t
t
SK
SK
t
t
t
JIT
F
SK
SK
t
REFSEL
REFSEL
(ω), t
t
t
t
t
JIT
JIT
) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.
t
SK
t
OFALL
t
SK
ODCV
ORISE
L
t
SK
L
V
t(φ)
) is the output to corresponding output skew between any two devices operating under the same conditions (V
NOM
RPW
FPW
(
1
2
(
(
is measured with all outputs selected for zero delay.
1
2
(ω)
DUTY
t
(
PD
(
(
OX
(
(
PER
(
L
(
(ω)
(ω)
PR
CC
HP
O
INV
INV
B
)
)
)
)
L
)
)
)
)
)
(
1
2
)
REFSEL
)
)
1
), t
L
(
REFSEL
Parameter
VCO Frequency Range
Reference Clock Pulse Width HIGH or LOW
Feedback Input Pulse Width HIGH or LOW
Output Matched Pair Skew
Output Skew (Rise-Rise, Fall-Fall, Nominal)
Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nominal-Divided, Divided-Divided)
Multiple Frequency Skew (Rise-Fall, Nominal-Divided, Divided-Divided)
Inverting Skew (Nominal-Inverted)
Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)
Process Skew
REF Input to FB Static Phase Offset
Output Duty Cycle Variation from 50%
Output Rise Time
Output Fall Time
Power-up PLL Lock Time
PLL Lock Time After Input Frequency Change
PLL Lock Time After Change in REF_SEL
PLL Lock Time After Change in REF_SEL (REF
PLL Lock Time After Asserting PD Pin
Cycle-to-Cycle Output Jitter (peak-to-peak)
Period Jitter (peak-to-peak)
Half Period Jitter (peak-to-peak, QFB/QFB only)
Duty Cycle Jitter (peak-to-peak)
HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level
QFB/QFB only
2
), and t
DDQ
/2.
L
(
PD
) are the times that are required before the synchronization is achieved. These specifications are valid only after V
(1,3.5)
(12)
(8)
(8)
(9)
(10)
(1,2,4)
(10)
(1,3)
(6)
(9)
(7)
(10)
(9,11)
(1,3)
(9)
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
1
(10, 12)
and REF
16
0
are different frequency)
(1,3,4)
(1,3,4)
(1,3,4)
(9)
DD
and V
V
DDQ
INDUSTRIAL TEMPERATURE RANGE
Min.
-100
-375
-275
see VCO Frequency Range Select Table
DDQ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
/2 - 150
1
1
, ambient temperature, air flow, etc.).
V
Typ.
DDQ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
/2
V
DDQ
THI
DD
Max
100
100
400
400
400
300
100
375
275
100
125
100
1.2
1.2
/2 + 150
—
—
50
75
75
/V
on REF to V
1
1
1
1
1
1
DDQ
is stable and
Unit
mV
ms
ms
ms
ms
μs
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ps
ps
ps
ps
THI
on