ICS9DB306BLLF IDT, Integrated Device Technology Inc, ICS9DB306BLLF Datasheet
ICS9DB306BLLF
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ICS9DB306BLLF Summary of contents
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PCI Express Jitter Attenuator G D ENERAL ESCRIPTION The ICS9DB306 is a high performance 1-to Differential-to-LVPECL Jitter Attenuator designed for HiPerClockS™ use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, ...
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ICS9DB306 Data Sheet ABLE IN ESCRIPTIONS ...
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ICS9DB306 Data Sheet BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY ...
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ICS9DB306 Data Sheet T 4D. LVPECL DC C ABLE HARACTERISTICS ...
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ICS9DB306 Data Sheet 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k The illustrated phase noise plot was taken using a low phase noise signal generator, the noise ...
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ICS9DB306 Data Sheet P ARAMETER CCA LVPECL V EE -1.3V ± 0.33V 3.3V LVPECL UTPUT OAD PCIEXC0:5x PCIEXT0:5x PCIEXC0:5y PCIEXT0:5y tsk( UTPUT KEW PCIEXC0:5 80% 20% PCIEXT0:5 t ...
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ICS9DB306 Data Sheet OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The ICS9DB306 ...
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ICS9DB306 Data Sheet IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and V input requirements. Figures show interface CMR examples for ...
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ICS9DB306 Data Sheet T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs ...
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ICS9DB306 Data Sheet S E CHEMATIC XAMPLE Figure 5 shows an example of ICS9DB306 application schematic. In this example, the device is operated at V The decoupling capacitor should be located as close as possible to the power pin. The ...
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ICS9DB306 Data Sheet This section provides information on power dissipation and junction temperature for the ICS9DB306. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS9DB306 is the sum of the core power ...
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ICS9DB306 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure calculate worst case power dissipation into ...
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ICS9DB306 Data Sheet T 7A ABLE VS IR LOW ABLE JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second ...
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ICS9DB306 Data Sheet ACKAGE UTLINE UFFIX FOR T 8A ABLE ACKAGE IMENSIONS ...
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ICS9DB306 Data Sheet ABLE RDERING NFORMATION ...
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ICS9DB306 Data Sheet ...
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ICS9DB306 Data Sheet www.IDT.com 6024 Silver Creek Valley Road Sales San Jose, CA 95138 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or ...