ICS8725AY-01LFT IDT, Integrated Device Technology Inc, ICS8725AY-01LFT Datasheet

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ICS8725AY-01LFT

Manufacturer Part Number
ICS8725AY-01LFT
Description
IC CLK GEN ZD 1:5 HSTL 32-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Clock Generatorr
Datasheet

Specifications of ICS8725AY-01LFT

Pll
Yes with Bypass
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
HSTL
Number Of Circuits
1
Ratio - Input:output
2:5
Differential - Input:output
Yes/Yes
Frequency - Max
700MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
630MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
8725AY-01LFT
B
8725AY-01
G
be configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to
700MHz. The reference divider, feedback divider and out-
put divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1,
1:1, 1:2, 1:4, 1:8. The external feedback allows the device
to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode,
the reference clock is routed around the PLL and into the
internal output dividers.
CLK_SEL
PLL_SEL
HiPerClockS™
IC S
nFB_IN
nCLK0
nCLK1
LOCK
ENERAL
FB_IN
CLK0
CLK1
SEL0
SEL1
SEL2
SEL3
MR
D
The ICS8725-01 is a highly versatile 1:5 Dif-
ferential-to-HSTL clock generator and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8725-01 has a fully integrated PLL and can
IAGRAM
D
Integrated
Circuit
Systems, Inc.
0
1
ESCRIPTION
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
PLL
,
÷64
www.icst.com/products/hiperclocks.html
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
F
• Five differential HSTL outputs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx pairs can accept the following differential
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
• Programmable dividers allow for the following output-to-input
• Static phase offset: ±100ps
• Cycle-to-cycle jitter: 25ps
• Output skew: 25ps
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
P
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
with configurable frequencies
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
packages
EATURES
IN
CLK_SEL
A
nCLK0
nCLK1
SSIGNMENT
CLK0
CLK1
SEL0
SEL1
MR
7mm x 7mm x 1.4mm package body
Z
1
2
3
4
5
6
7
8
ERO
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1:5 D
32-Lead LQFP
ICS8725-01
D
Y Package
Top View
ELAY
IFFERENTIAL
C
ICS8725-01
LOCK
REV. B NOVEMBER 15, 2005
G
24
23
22
21
20
19
18
17
-
TO
ENERATOR
V
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
-HSTL
DDO
DDO

Related parts for ICS8725AY-01LFT

ICS8725AY-01LFT Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS8725- highly versatile 1:5 Dif ferential-to-HSTL clock generator and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8725-01 has a ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc ABLE ONTROL NPUT UNCTION ...

Page 4

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S ...

Page 5

Integrated Circuit Systems, Inc. T 4D. HSTL DC C ABLE HARACTERISTICS ...

Page 6

Integrated Circuit Systems, Inc. P ARAMETER 3.3V ± 5% 1.8V ± 0. DDA V DDO HSTL GND 0V 3.3V C /1. ORE UTPUT OAD nQx nQ nQy Qy tsk( UTPUT ...

Page 7

Integrated Circuit Systems, Inc OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8725-01 provides separate power supplies to isolate any high switching noise ...

Page 8

Integrated Circuit Systems, Inc IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show inter- PP ...

Page 9

Integrated Circuit Systems, Inc AYOUT UIDELINE The schematic of the ICS8725-01 layout example is shown in Figure 4A. The ICS8725-01 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as ...

Page 10

Integrated Circuit Systems, Inc. The following component footprints are used in this layout example: All the resistors and capacitors are size 0603 OWER AND ROUNDING Place the decoupling capacitors C1, C6, C2, C4, and C5, as close as ...

Page 11

Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS8725-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8725-01 is the sum of the core ...

Page 12

Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. F IGURE T o calculate worst case ...

Page 13

Integrated Circuit Systems, Inc. 8. θ ABLE VS IR LOW ABLE FOR JA θ θ θ θ θ Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs ...

Page 14

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR ABLE ...

Page 15

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

Page 16

Integrated Circuit Systems, Inc ...

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