IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 112
IDT82V3288BCG
Manufacturer Part Number
IDT82V3288BCG
Description
IC PLL WAN 3E STRATUM 2 208CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3288BCG.pdf
(170 pages)
Specifications of IDT82V3288BCG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CABGA
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3288BCG
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Quantity
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Part Number:
IDT82V3288BCG
Manufacturer:
IDT
Quantity:
200
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IN3_IN4_STS - Input Clock 3 & 4 Status
Address: 44H
Type: Read
Default Value: X110X110
Programming Information
IDT82V3288
Bit
7
6
5
4
3
2
1
0
7
-
IN4_FREQ_HAR
IN4_NO_ACTIVITY_ALARM
IN3_NO_ACTIVITY_ALARM
IN4_FREQ_HARD_ALARM
IN3_FREQ_HARD_ALARM
D_ALARM
IN4_PH_LOCK_ALARM
IN3_PH_LOCK_ALARM
6
Name
-
-
IN4_NO_ACTIVI
TY_ALARM
5
Reserved.
This bit indicates whether IN4 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN4 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN4 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second ) which starts from when the alarm is raised.
Reserved.
This bit indicates whether IN3 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN3 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN3 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second ) which starts from when the alarm is raised.
IN4_PH_LOCK_
ALARM
4
112
3
-
IN3_FREQ_HAR
D_ALARM
Description
2
IN3_NO_ACTIVI
TY_ALARM
1
IN3_PH_LOCK_
March 14, 2007
ALARM
0
WAN PLL
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