CY28329ZXC Cypress Semiconductor Corp, CY28329ZXC Datasheet

IC CLOCK SYNTH SS 56-TSSOP

CY28329ZXC

Manufacturer Part Number
CY28329ZXC
Description
IC CLOCK SYNTH SS 56-TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Clock Driver, Clock/Frequency Synthesizer, Fanout Distribution, Spread Spectrum Clock Generatorr
Datasheet

Specifications of CY28329ZXC

Pll
Yes
Input
LVTTL, Crystal
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:22
Differential - Input:output
No/Yes
Frequency - Max
133MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP II
Frequency-max
133MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY28329ZXC
Manufacturer:
CY
Quantity:
81
Part Number:
CY28329ZXCT
Manufacturer:
FINISAR
Quantity:
101
Cypress Semiconductor Corporation
Document #: 38-07040 Rev. *E
Features
• Multiple output clocks at different frequencies
• Spread Spectrum clocking (down spread)
• Power-down features (PCI_STOP#, PD#)
• Three Select inputs (Mode select & IC Frequency
• OE and Test Mode support
• 56-pin SSOP package and 56-pin TSSOP package
Logic Block Diagram
— Four pairs of differential CPU outputs, up to 133 MHz
— Ten synchronous PCI clocks, three free-running
— Six 3V66 clocks
— Two 48-MHz clocks
— One reference clock at 14.318 MHz
— One VCH clock
Select)
VTTPWRGD#
PCI_STOP#
SDATA
SCLK
Mult0
S1:2
X1
X2
PD#
Gate
XTAL
PLL 1
PLL 2
OSC
SMBus
Logic
133-MHz Spread Spectrum Clock Synthesizer/Driver
Network
Divider
PWR
PWR
PWR
PWR
PLL Ref Freq
PWR
/2
PWR
Control
Clock
Stop
3901 North First Street
VDD_48MHz
VDD_3V66
3V66_0
3V66_[2:]4/
66BUFF0:2
USB (48MHz)
DOT (48MHz)
VDD_REF
REF
VDD_CPU
CPU[0:3]
VDD_PCI
3V66_5/ 66IN
VCH_CLK/ 3V66_1
CPU[0:3]#
PCI_F[0:2]
PCI0:6
Benefits
• Motherboard clock generator
• Enables reduction of EMI and overall system cost
• Enables ACPI compliant designs
• Supports up to four CPU clock frequencies
• Enables ATE and “bed of nails” testing
• Widely available, standard package enables lower cost
with Differential CPU Outputs
— Support Multiple CPUs and a chipset
— Support for PCI slots and chipset
— Supports AGP and Hub Link
— Supports USB host controller and graphic controller
— Supports ISA slots and I/O chip
66BUFF2/3V66_4
66BUFF0/3V66_2
66BUFF1/3V66_3
San Jose
VTTPWRGD#
66IN/3V66_5
GND_CORE
VDD_CORE
XTAL_OUT
GND_3V66
VDD_3V66
GND_REF
VDD_REF
GND_PCI
GND_PCI
VDD_PCI
VDD_PCI
XTAL_IN
Pin Configurations
PCI_F0
PCI_F1
PCI_F2
PCI6
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
PD#
,
SSOP and TSSOP
CA 95134
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Top View
Revised January 19, 2005
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_ 48 MHz
GND_ 48 MHz
DOT
REF
S1
CPU3
CPU3#
CPU0
CPU0#
VDD_CPU
CPU1
CPU1#
GND_CPU
VDD_CPU
CPU2
CPU2#
MULT0
IREF
GND_IREF
S2
USB
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_3V66
GND_3V66
SCLK
SDATA
408-943-2600
CY28329

Related parts for CY28329ZXC

CY28329ZXC Summary of contents

Page 1

... PWR PLL 2 PWR SDATA SMBus SCLK Logic Cypress Semiconductor Corporation Document #: 38-07040 Rev. *E with Differential CPU Outputs Benefits • Motherboard clock generator — Support Multiple CPUs and a chipset — Support for PCI slots and chipset — Supports AGP and Hub Link — ...

Page 2

Pin Description Name Pins REF 56 XTAL_IN 2 XTAL_OUT 3 CPU, CPU [0:3]# 44, 45, 48, 49, 51, 52, 53, 54 3V66_0 33 3V66_1/VCH 35 66IN/3V66_5 24 66BUFF [0:2] 21, 22, 23 /3V66 [2:4] PCI_F [0: PCI ...

Page 3

Function Table CPU 3V66[0:1 (MHz) MHz 100 MHz 66 MHz 1 1 133 MHz 66 MHz 0 0 100 MHz 66 MHz 0 1 133 MHz 66 MHz Mid 0 Hi-Z Hi-Z Mid 1 TCLK/2 ...

Page 4

Serial Data Interface (SMBus) To enhance the flexibility and function of the clock synthesizer, a two-signal SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can ...

Page 5

Data Byte 1: Bit Pin# Name Bit 7 – Bit 6 53, 54 CPU3 CPU3# Bit 5 – – Bit 4 – – Bit 3 – – Bit 2 44, 45 CPU2 CPU2# Bit 1 48, 49 CPU1 CPU1# Bit ...

Page 6

Data Byte 4: Bit Pin# Name Bit 7 – Bit 6 – Bit 5 33 3V66_0 Bit 4 35 3V66_1/VCH Bit 3 24 66IN/3V66_5 Bit 2 23 66BUFF2 Bit 1 22 66BUFF1 Bit 0 21 66BUFF0 Data Byte 5: Bit ...

Page 7

Absolute Maximum Conditions (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage ............................................ –0. Operating Conditions over which electrical parameters are guaranteed Parameter ...

Page 8

Switching Characteristics Over the Operating Range Parameter Output t All Output Duty Cycle 1 t CPU Rise Time 2 t USB, REF, Rising Edge Rate 2 DOT t PCI, 3V66 Rising Edge Rate 2 t CPU Fall Time 3 t ...

Page 9

Definition and Application of VTTPWRGD# Signal VRM8.5 VTTPWRGD# CLOCK S0 GENERATOR S1 Document #: 38-07040 Rev. *E Vtt VTTPWRGD# BSEL0 3.3V 3.3V NPN 10K 10K CY28329 CPU BSEL1 3.3V 10K GMCH 10K Page ...

Page 10

Switching Waveforms Duty Cycle Timing (Single-Ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew ...

Page 11

Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK VDD and POR Timing Document #: 38-07040 Rev 1.5V VDD 1.5V POR t 10 CY28329 ...

Page 12

VTTPWRGD# Timing Diagrams GND VRM 5/12V PWR_GD VID [3:0] BSEL [1:0] VTTPWRGD FROM VRM VCC CPU CORE VTTPWRGD VCC CLOCK GEN State 0 CLOCK STATE OFF CLOCK VCO OFF CLOCK OUTPUTS GND VRM 5/12V PWRGD VID [3:0] BSEL [1:0] PWRGD ...

Page 13

PD# Assertion 66BUFF PCI PCI_F (APIC) PD# CPU CPU# 3V66 66IN USB REF PD# Deassertion 66BUFF1/GMCH 66BUFF[0:2] PCI PCI_F (APIC) PD# CPU CPU# 3V66 66IN USB REF Document #: 38-07040 Rev. *E Power Down Rest of Generator 10–30 µs min. ...

Page 14

Layout Example +3.3V Supply FB 10 µF 0.005 µ VDDQ3 1.0 - 4.7KΩ Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S Ceramic Caps C1 = 10–22 µ VIA ...

Page 15

... Small Shrunk Outline Package (SSOP) CY28329OXCT 56-Pin Small Shrunk Outline Package (SSOP) -Tape and Reel CY28329ZXC 56-Pin Thin Small Shrunk Outline Package (TSSOP) CY28329ZXCT 56-Pin Thin Small Shrunk Outline Package (TSSOP) Document #: 38-07040 Rev 15, 20, 31, 36, 41 14, 19,32,37, 46, 50 CY28329 ...

Page 16

... Document #: 38-07040 Rev. *E © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 17

Document History Page Document Title: CY28329 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Document Number: 38-07040 REV. ECN NO. Issue Date ** 115133 04/26/02 *A 122733 12/14/02 *B 127128 06/13/03 *C 127899 06/26/03 *D 128179 06/27/03 *E 310457 ...

Related keywords