CY29773AXI Cypress Semiconductor Corp, CY29773AXI Datasheet - Page 2

• Manufacturer Part Number: CY29773AXI
• Description: IC CLK ZDB 14OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr
• Series: Spread Aware™r

Specifications of CY29773AXI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 125 MHz
• Minimum Input Frequency: 5 MHz
• Output Frequency Range: 8.3 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07573 Rev. *A
Pin Description
11
12
9
10
44,46,48,50
32,34,36,38
16,18,21,23
29
31
25
6
2
8
7
52
14
5,26,27
42,43
40,41
19,20
3
4
45,49
33,37
22,17
13
28
1
15,24,30,35,39,47,51 VSS
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Pin
[1]
PECL_CLK
PECL_CLK#
TCLK0
TCLK1
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
FB_IN
SYNC
PLL_EN
MR#/OE
TCLK_SEL
REF_SEL
VCO_SEL
INV_CLK
FB_SEL(2:0) I, PU
SELA(1,0)
SELB(1,0)
SELC(1,0)
SCLK
SDATA
VDDQA
VDDQB
VDDQC
AVDD
VDD
AVSS
Name
Supply
Supply
Supply
Supply
Supply
Supply
Supply
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I/O
O
O
O
O
O
I
LVCMOS LVCMOS/LVTTL reference clock input.
LVCMOS LVCMOS/LVTTL reference clock input.
LVCMOS Clock output bank A.
LVCMOS Clock output bank B.
LVCMOS Clock output bank C.
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This
LVCMOS Synchronous pulse output. This output is used for system synchro-
LVCMOS PLL enable/bypass input. When Low, PLL is disabled/bypassed and
LVCMOS Master reset and Output enable/disable input. See Table 2.
LVCMOS LVCMOS Clock reference select input. See Table 2. Function Table
LVCMOS LVCMOS/LVPECL Reference select input. See Table 2. Function
LVCMOS VCO Operating frequency select input. See Table 2. Function Table
LVCMOS QC(2,3) Phase selection input. See Table 2. Function Table (Config-
LVCMOS Feedback divider select input. See Table 6.
LVCMOS Frequency select input, Bank A. See Table 3. Function Table (Bank
LVCMOS Frequency select input, Bank B. See Table 4. Function Table (Bank
LVCMOS Frequency select input, Bank C. See Table 5. Function Table (Bank
LVCMOS Serial clock input.
LVCMOS Serial data input.
LVPECL LVPECL reference clock input.
LVPECL LVPECL reference clock input.
Ground
Ground
Type
VDD
VDD
VDD
VDD
VDD
input should be at the same voltage rail as input reference clock. See
Table 1. Frequency Table.
nization.
the input clock connects to the output dividers.
Function Table (Configuration Controls).
(Configuration Controls).
Table (Configuration Controls).
(Configuration Controls).
uration Controls).
A).
B).
C).
2.5V or 3.3V Power supply for bank A output clocks.
2.5V or 3.3V Power supply for bank B output clocks.
2.5V or 3.3V Power supply for bank C output clocks.
2.5V or 3.3V Power supply for PLL.
2.5V or 3.3V Power supply for core and inputs.
Analog Ground.
Common Ground.
Description
[2,3]
[2,3]
CY29773
[2,3]
[2,3]
[2,3]
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