CY29773AXI Cypress Semiconductor Corp, CY29773AXI Datasheet - Page 3

• Manufacturer Part Number: CY29773AXI
• Description: IC CLK ZDB 14OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr
• Series: Spread Aware™r

Specifications of CY29773AXI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 125 MHz
• Minimum Input Frequency: 5 MHz
• Output Frequency Range: 8.3 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07573 Rev. *A
Table 1. Frequency Table
Table 2. Function Table (Configuration Controls)
Table 3. Function Table (Bank A)
Table 4. Function Table (Bank B)
÷4
÷6
÷8.
÷10
÷12
÷16
÷20
÷24
÷32
÷40
TCLK_SEL
VCO_SEL
REF_SEL
INV_CLK
Feedback Output
MR#/OE
PLL_EN
VCO_SEL
VCO_SEL
Control
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Divider
Default
1
1
1
1
1
1
SELA1
SELB1
0
0
1
1
0
0
1
1
TCLK0, TCLK1
TCLK0
VCO÷2 (low input frequency range)
Bypass mode, PLL disabled. The input clock connects to the
output dividers
QC2 and QC3 are in phase with QC0 and QC1
Outputs disabled (three-state) and reset of the device. During
reset/output disable the PLL feedback loop is open and the VCO
running at its minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during power-up.
0
0
1
1
0
0
1
1
Input Clock * 4
Input Clock * 6
Input Clock * 8
Input Clock * 10
Input Clock * 12
Input Clock * 16
Input Clock * 20
Input Clock * 24
Input Clock * 32
Input Clock * 40
VCO
SELA0
SELB0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QA(0:3)
QB(0:3)
50 MHz to 125 MHz
33.3 MHz to 83.3 MHz
25 MHz to 62.5 MHz
20 MHz to 50 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
10 MHz to 25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
5 MHz to 12.5 MHz
÷12
÷16
÷24
÷12
÷12
÷16
÷20
÷10
÷8
÷4
÷6
÷8
÷8
÷4
÷6
÷8
0
Input Frequency Range
(AVDD = 3.3V)
Table 5. Function Table (Bank C)
VCO_SEL
0
0
0
0
1
1
1
1
SELC1
TCLK1
VCO÷1 (high input frequency range)
PLL enabled. The VCO output
connects to the output dividers
QC2 and QC3 are inverted (180° phase
shift) with respect to QC0 and QC1
Outputs enabled
PECL_CLK
0
0
1
1
0
0
1
1
50 MHz to 95 MHz
33.3 MHz to 63.3 MHz
25 MHz to 47.5 MHz
20 MHz to 38 MHz
16.6 MHz to 31.6 MHz
12.5 MHz to 23.75 MHz
10 MHz to19 MHz
8.3 MHz to 15.8 MHz
6.25 MHz to 11.8 MHz
5 MHz to 9.5 MHz
Input Frequency Range
(AVDD = 2.5V)
SELC0
0
1
0
1
0
1
0
1
1
CY29773
Page 3 of 13
QC(0:3)
÷12
³16
÷4
÷8
÷2
÷4
÷6
÷8