CY29773AXI Cypress Semiconductor Corp, CY29773AXI Datasheet - Page 8

• Manufacturer Part Number: CY29773AXI
• Description: IC CLK ZDB 14OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr
• Series: Spread Aware™r

Specifications of CY29773AXI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 125 MHz
• Minimum Input Frequency: 5 MHz
• Output Frequency Range: 8.3 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07573 Rev. *A
AC Electrical Specifications
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The CY29773 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
f
f
f
DC
t
t
t
tsk(B)
t
t
BW
t
t
t
t
MAX
MAX
SCLK
r
(φ)
sk(O)
PLZ, HZ
PZL, ZH
JIT(CC)
JIT(PER)
JIT(φ)
LOCK
, t
Parameter
f
Maximum Output Frequency
Maximum Output Frequency
(continued)
Serial Clock Frequency
Output Duty Cycle
Output Rise/Fall times
Propagation Delay (static phase
offset)
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
(–3 dB)
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
Description
(V
DD
= 3.3V ±5%, T
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
f
f
0.55V to 2.4V
TCLK to FB_IN, same VDD
PCLK to FB_IN, same VDD
Skew within Bank A
Skew within Bank B
Skew within Bank C
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
Same frequency (125 MHz)
RMS (1σ)
Same frequency
Multiple frequencies
Same frequency (125 MHz)
RMS (1σ)
Same frequency
Multiple frequencies
I/O same V
MAX
MAX
A
< 100 MHz
> 100 MHz
= –40°C to +85°C)
Condition
DD
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. Figure 1 illus-
trates various waveforms for the SYNC output. Note that the
SYNC output is defined for all possible combinations of the QA
and QC outputs even though under some relationships the
lower frequency clock could be used as a synchronizing
signal.
[7]
–125
–125
Min.
33.3
16.6
12.5
100
8.3
0.1
50
25
20
10
48
45
––
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.3–2.0
0.7–1.3
0.9–1.3
0.6–1.1
0.6–0.9
0.4–0.6
0.6–0.9
Typ.
45
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7
–
–
6
–
–
–
31.25
Max.
83.3
62.5
41.6
20.8
200
125
125
125
100
150
325
100
375
225
150
1.0
50
25
20
52
55
75
30
30
75
8
8
–
–
–
–
–
–
–
1
CY29773
Page 8 of 13
MHz
MHz
MHz
MHz
Unit
ms
ns
ns
ns
ps
ps
ps
ps
ps
ps
%