LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 16

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

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Bench Test Setups
SENSITIVITY MEASUREMENT PROCEDURE
Sensitivity is defined as the power level limits beyond which
the output of the counter being tested is off by 1 Hz or more
of its expected value. It is typically measured over frequency,
voltage, and temperature. In order to test sensitivity, the
MUX[3:0] word is programmed to the appropriate value. The
counter value is then programmed to a fixed value and a
frequency counter is set to monitor the frequency of this pin.
The expected frequency at the Ftest/LD pin should be the
signal generator frequency divided by twice the correspond-
ing counter value. The factor of two comes in because the
LMX2471 has a flip-flop which divides this frequency by two
to make the duty cycle 50% in order to make it easier to read
with the frequency counter. The frequency counter input
impedance should be set to high impedance. In order to
perform the measurement, the temperature, frequency, and
voltage is set to a fixed value and the power level of the
signal is varied. The power level at the part is assumed to be
4 dB less than the signal generator power level. This ac-
Frequency Input Pin
OSCin
FinRF
FinIF
DC Blocking Capacitor
1000 pF
100 pF
(Continued)
47 pF
Corresponding Counter
RF_R / 2
RF_N / 2
IF_N / 2
16
counts for 1 dB for cable losses and 3 dB for the pad. The
power level range where the frequency is correct at the
Ftest/LD pin to within 1 Hz accuracy is recorded for the
sensitivity limits. The temperature, frequency, and voltage
can be varied in order to produce a family of sensitivity
curves. Since this is an open-loop test, the charge pump is
set to TRI-STATE and the unused side of the PLL (RF or IF)
is powered down when not being tested. For this part, there
are actually four frequency input pins, although there is only
one frequency test pin (Ftest/LD). The conditions specific to
each pin are show above. The LMX2471 has a test bit that
may be useful in debugging sensitivity problems at the
FinRF pin. The location of this bit is R6[22] and should
always be set to 0 for normal operation. If this bit is set to 1,
then the sensitivity is degraded. When one suspects a sen-
sitivity problem, try setting this bit to 1 and see what hap-
pens. If the problem is unaffected, it is likely not to be a
sensitivity problem at the FinRF pin.
Default Counter Value
500
500
50
MUX Value
14
15
13
20072170
OSC
0
X
X