LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 32

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

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REGISTER 23 22 21 20 19
Programming Description
2.7 R6 REGISTER
2.7.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
2.7.2 OSC -- Differential Oscillator Mode Enable
This bit selects between single-ended and differential mode for the OSCin and OSCout* pins. When this bit is set to 0, the RF R
and IF R counters are driven in a single-ended fashion through the OSCin pin. Note that the OSCin and OSCout* pin can not be
used to drive a crystal. When this bit is set to 1, the OSCin and OSCout* pins are used to drive these R counters differentially.
In some cases, spur performance may be better when this is set to differential mode, even if the R counters are being driven in
a single-ended fashion. Current consumption in differential mode is slightly higher than when in single-ended mode.
2.7.3 OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled TCXO frequency presented to the IF R counter is unaffected. Phase
noise added by the doulber is negligible.
2.7.4 ATPU -- PLL Automatic Power Up
This word enables the PLLs to be automatically powered up when their respective registers are written to. Note that since the IF
Powerdown bit is in the IF register, there is no need to have an ATPU function activated by the R2 word.
R6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATPU
0
1
2
3
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
MUX[3:0]
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
CPT
Powers up when R0 is written to
Powers up when R0 is written to
RF_
18
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPP
RF_
17
No auto power up
(Continued)
RF PLL
CPT
IF_
16
High Impedance
Output Type
Open Drain
Open Drain
Open Drain
CPP
IF_
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
15
FDM FM[1:0]
14
32
13
Reserved
12 11 10
General purpose output, Logical “High” State
General purpose output, Logical “Low” State
ATPU
[1:0]
Powers up when R0 is written to
RF & IF Analog Lock Detect
RF & IF Analog Lock Detect
OSC
RF & IF Digital Lock Detect
2X
RF R Divider divided by 2
RF N Divider divided by 2
IF R Divider divided by 2
IF N Divider divided by 2
9
RF Analog Lock Detect
RF Analog Lock Detect
RF Digital Lock Detect
IF Analog Lock Detect
IF Analog Lock Detect
IF Digital Lock Detect
Output Description
OSC
No auto power up
No auto power up
8
Disabled
IF PLL
7 6 5 4
MUX
[3:0]
C3 C2 C1 C0
3
1
2
0
1
1
0
1