LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 33

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

Programming Description
2.7.5 FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the
carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least
one greater than the order of the delta-sigma modulator in order to allow for sufficient roll-off.
2.7.6 FDM -- Fractional Denominator Mode
When this bit is set to 0, the part operates with a 12- bit fractional denominator. For most applications, 12-bit mode should be
adequate, but for those applications requiring ultra fine tuning resolution, there is 22-bit mode. Note that the PLL may consume
slightly more current when it is in 22-bit mode.
2.7.7 IF_CPP -- IF PLL Charge Pump Polarity
When this bit is set to 1, the phase detector polarity for the IF PLL charge pump is positive. Otherwise set this bit to 0 for a
negative phase detector polarity
2.7.8 IF_CPT -- IF PLL Charge Pump TRI-STATE Mode
This bit enables the user to put the charge pump in a TRI-STATE ( high impedance ) condition. Note that if there is a conflict, the
ATPU bit overrides this bit.
2.7.9 RF_CPP -- RF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit to 0 for a negative phase
detector polarity.
2.7.10 RF_CPT -- RF PLL Charge Pump TRI-STATE Mode
This bit enables the user to put the charge pump in a TRI-STATE ( high impedance) condition. Note that if there is a conflict, the
ATPU bit overrides this bit.
FDM
0
1
FM
Bits for Fractional Denominator/Numerator
0
1
2
3
RF_CPT
RF_CPT
0
1
0
1
12-bit
22-bit
Disable the delta-sigma modulator. Recommended for test use only.
(Continued)
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
Fractional PLL mode with a 4th order delta-sigma modulator
33
Maximum Size of Fractional Denominator/Numerator
Function
Charge Pump State
Charge Pump State
TRI-STATE
TRI-STATE
ACTIVE
Active
4194303
4095
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