LMX2471SLEX National Semiconductor, LMX2471SLEX Datasheet - Page 28

• Manufacturer Part Number: LMX2471SLEX
• Description: IC PLL LP 3.6GHZ/1.7GHZ 24-CSP
• Manufacturer: National Semiconductor
• Type: PLL Frequency Synthesizer, Delta Sigmar

Specifications of LMX2471SLEX

• Pll: Yes with Bypass
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:3
• Differential - Input:output: Yes/No
• Frequency - Max: 3.6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-Laminate UTCSP
• Frequency-max: 3.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LMX2471SLEXTR

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REGISTER
Programming Description
2.3 R2 REGISTER
2.3.1 IF_N[16:0] -- IF N Divider Value
The IF N divider is a classical dual modulus prescaler with a selectable 8/9 or 16/17 modulus. The IF_N value is determined by
the IF_A , IF_B, and IF_P values. Note that the IF_P word can assume a value of 8 or 16. The RF_A and RF_B counter values
can be determined in accordance with the following equations.
B = N div P
A = N mod P
B≥A is required in order to have a legal N divider ratio
Here the div operator is defined as the division of two numbers with the remainder disregarded and the mod operator is defined
as the remainder as a result of this division. For the purposes of programming, it turns out that the register value is just the binary
representation of the N value, with the exception that the 4
prescaler is used.
IF_N Programming with the 8/9 Prescaler
RF_N Programming with 16/17 Prescaler
2.3.2 IF_CPG -- IF Charge Pump Gain
This bit determines the magnitude of the IF charge pump current
2.3.3 IF_P -- IF Prescaler Value
This bit selects which prescaler will be used for the IF N counter.
2.3.4 IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the output of the IF PLL
charge pump is set to a TRI-STATE mode. If the IF_CPT bit is set to 0, then the power down state is synchronous and will not
occur until the charge pump is off. If the IF_CPT bit is set to 1, then the power down will occur immediately regardless of the state
of the IF PLL charge pump.
N Value
N Value
131071
R2
48-239
65535
24-55
≤47
240
<
...
56
...
24
IF_PD IF_P IF_CPG
23
0
.
0
1
.
0
1
22
.
IF_CPG
0
1
.
0
1
IF_P
0
1
0
1
.
0
1
.
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
21
N values less than or equal to 47 are prohibited because IF_B≥3 is required.
0
1
.
0
1
.
Legal divide ratios in this range are: 48-51, 64-68, 80-85, 96-102
Legal divide ratios in this range are: 24-27, 32-36, 40-45, 48-54
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
N Values Below 24 are prohibited since IF_B≥3 is required.
0
1
.
0
1
.
(Continued)
0
1
.
0
1
.
IF_B
IF_B
0
1
.
0
1
.
th
0
1
.
0
1
28
.
LSB is not used and must be programmed to 0 when the 8/9
IF_N[16:0]
IF_N[16:0]
IF_N[17:0]
0
1
0
1
.
.
IF Charge Pump Current (mA)
0
1
0
1
.
.
16 (16/17 Prescaler)
IF Prescaler Value
1
1
1
1
.
.
8 (8/9 Prescaler)
High (4 mA)
Low (1 mA)
1
1
1
1
.
.
1
1
1
1
.
.
0
1
0
0
0
.
0
1
0
1
.
.
C3 C2 C1 C0
IF_A
IF_A
3
0
0
1
0
1
.
2
0
.
1
1
0
1
0
1
.
.
0
1