SI4133W-BM Silicon Laboratories Inc, SI4133W-BM Datasheet
SI4133W-BM
Specifications of SI4133W-BM
Related parts for SI4133W-BM
SI4133W-BM Summary of contents
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... Phase RF1 ÷ N Phase RF2 ÷ N Phase IFDIV IF ÷ N Copyright © 2002 by Silicon Laboratories Ordering Information: See page 28. Pin Assignments Si4133W-BM GNDR RFLD RFLC GNDR NC GNDR GNDR Patents pending RFOUT RFLC RFLD IFOUT IFLA IFLB Si4133W-DS11 GNDI IFLB IFLA GNDD VDDD ...
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... Si4133W 2 Rev. 1.1 ...
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... Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RF and IF Outputs (RFOUT and IFOUT Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Auxiliary Output (AUXOUT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Descriptions: Si4133W- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package Outline: Si4133W- Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Rev. 1.1 Si4133W Page 3 ...
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... Si4133W Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. ...
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... For signals SCLK, SDATA, SENB, and PWDNB. 3. For signal AUXOUT. Symbol Test Condition RF1 and IF operating PWDNB = –500 µ 500 µ Rev. 1.1 Si4133W Min Typ Max Unit — 23 27.5 mA — — — 9 11.5 mA — 5 — µA 0.7 V — — — — 0 –10 — 10 µA –10 — ...
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... Si4133W Table 4. Serial Interface Timing (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time 2 SDATA Setup Time to SCLK↑ 2 SDATA Hold Time from SCLK↑ 2 SENB↓ to SCLK↑ Delay Time 2 SCLK↑ ...
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... S CLK 50% 20% Figure 1. SCLK Timing Diagram CLK D17 t en1 Figure 2. Serial Interface Timing Diagram First bit c loc ked Figure 3. Serial Interface Format clk t hold D16 D15 data address field Rev. 1.1 Si4133W en3 t en2 t w Last bit clocked field 7 ...
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... Si4133W Table 5. Si4133W RF and IF Synthesizer Characteristics (V = 2 – ° Parameter XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency 3 RF1 VCO Tuning Range RF2 VCO Center Frequency Range 5 RF2 Tuning Range from f CEN IF VCO Center Frequency Range IFOUT Tuning Range from f ...
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... Table 5. Si4133W RF and IF Synthesizer Characteristics (Continued 2 – ° Parameter IF Phase Noise IF Integrated Phase Error RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Output Power Level IFOUT Output Power Level IF Output Voltage Level RF1 Output Reference Spurs RF2 Output Reference Spurs ...
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... Si4133W RF and nthes iz ers s ettled to w ithin 0.1 ppm f requenc y error. t pup Figure 4. Software Power Management Timing Diagram 10 t pdn DNB Figure 5. Hardware Power Management Timing Diagram Rev. 1.1 RF and IF synthesizers settled to within 0.1 ppm frequency error pup pdn ...
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... Figure 6. Typical Transient Response RF1 at 2.4 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.1 Si4133W 11 ...
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... Si4133W -60 -70 -80 -90 -100 -110 -120 -130 -140 1.E+02 Figure 7. Typical RF1 Phase Noise at 2.4 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 2.4 GHz with 200 kHz Phase Detector Update Frequency 12 1.E+03 1.E+04 Offset Frequency (Hz) Rev ...
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... Offset Frequency (Hz) Figure 9. Typical RF2 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency 1.E+04 1.E+05 Rev. 1.1 Si4133W 1.E+06 13 ...
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... Si4133W -60 -70 -80 -90 -100 -110 -120 -130 -140 1.E+02 Figure 11. Typical IF Phase Noise at 800 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 800 MHz with 200 kHz Phase Detector Update Frequency 14 1.E+03 1.E+04 O ffse t Fre que nc y (Hz) Rev ...
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... MHz. V DDI 30 Ω * µ 0.022 GNDI 20 IFLB 19 IFLA 18 Si4133W G NDD 17 VDDD 16 G NDD 15 XIN µ F Figure 13. Application Diagram Rev. 1.1 Si4133W 40 nH 560 pF IFOUT Printed Trace Inductor V DD 0.022 µ F 560 pF External Clock AUXOUT 2 nH 560 pF RFOUT 15 ...
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... RF output can be programmed to service two widely separated frequency bands by programming the corresponding N-Divider. The Si4133W has the RF1 VCO optimized to operate from 2.3 to 2.6 GHz, while the RF2 VCO is optimized to have its center frequency set between 750 MHz and 1 ...
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... CEN ⋅ 2π TOT or 1 ---------------------------------------------------------------------- f = CEN ( 2π PKG EXT Table 6 summarizes the characteristics of each VCO. Table 6. Si4133W-BM VCO Characteristics VCO Fcen Range Cnom Lpkg (MHz) (pF) (nH) Min Max RF2 789 1619 5.1 1.6 IF 526 952 6.8 1.6 L PKG 2 L PKG 2 Figure 14 ...
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... Si4133W executes the self- tuning algorithm. Thereafter the PLL controls the output frequency. Because of the unique architecture of the Si4133W PLLs, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. Thus, the total time after power- change ...
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... XIN pin through a 560 pF capacitor. Power Down Modes Table 10 summarizes the power down functionality. The Si4133W can be powered down by taking the PWDNB pin low or by setting bits in the Powerdown register (Register 2). When the PWDNB pin is low, the Si4133W Rev. 1.1 Si4133W Table 9. L Values ...
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... Powerdown register bits. The reference frequency amplifier, IF, and RF sections of the Si4133W circuitry can be individually powered down by setting the Power Down register bits PDIB and PDRB low. Also, setting the AUTOPDB bit the Main Configuration register (Register 0) is equivalent to setting both bits in the Powerdown register to 1 ...
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... Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior. Table 11. Register Summary Bit Bit Bit Bit Bit Bit Bit Bit AUXSEL[1:0] IFDIV[1: [17:0] RF1 N [16:0] RF2 Rev. 1.1 Si4133W Bit Bit Bit Bit Bit Bit LPWR AUTO PDB [1:0] K [1: PDIB [15:0] R [12:0] RF1 R [12:0] RF2 R [12:0] IF Bit 0 0 ...
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... Si4133W Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name AUXSEL[1:0] Bit Name 17:14 Reserved 13:12 AUXSEL[1:0] 11:10 IFDIV[1:0] 9:6 Reserved 5 LPWR 4 Reserved 3 AUTOPDB 2 Reserved 1 Reserved 0 Reserved IFDIV[1:0] Function Program to zero. Auxiliary Output Pin Definition. ...
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... IF Phase Detector Gain Constant. N Value K PI <1024 = 00 1024–2047 = 01 2048–4095 = 10 >4095 = 11 RF2 Phase Detector Gain Constant. N Value K P2 <2048 = 00 2048–4095 = 01 4096–8191 = 10 >8191 = 11 RF1 Phase Detector Gain Constant. N Value K P1 <4096 = 00 4096–8191 = 01 8192–16383 = 10 >16383 = 11 Rev. 1.1 Si4133W [1:0] K [1:0] K [1: ...
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... Si4133W Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Note: Enabling any PLL with PDIB or PDRB will automatically power on the reference amplifier. Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011 ...
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... R-Divider for RF2 Synthesizer. RF2 R RF2 [15:0] IF Program to zero. N-Divider for IF Synthesizer RF1 Function can be any value from 7 to 8189 8189 8189 8189 RF2 Function can be any value from 7 to 8189 8189 8189 8189 if K Rev. 1.1 Si4133W Function [12: [12: ...
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... Si4133W Register 8. IF R-Divider Address Field (A[3:0]) = 1000 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:13 Reserved Program to zero. 12:0 R [12:0] R-Divider for IF Synthesizer Function can be any value from 7 to 8189 8189 8189 8189 if K Rev. 1.1 ...
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... Pin Descriptions: Si4133W-BM Pin Number(s) Name Description 1,4, 6–9, 28 GNDR Common ground for RF analog circuitry 2, 3 RFLC, RFLD Pins for inductor connection to RF2 VCO connect 10 RFOUT Radio frequency (RF) output of the selected RF VCO 11 VDDR Supply voltage for the RF analog circuitry 12 AUXOUT Auxiliary output ...
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... Si4133W Ordering Guide Ordering Part Number Si4133W-BM 28 Description Operating Temperature 2.4 GHz/RF2/IFOUT Rev. 1.1 o – ...
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... Package Outline: Si4133W- D TOP VIEW FOR ODD TERMINAL/SIDE Figure 18. 28-Pin Micro Leadframe Package (MLP E1/2 E θ SECTION "C–C" SCALE: NONE e FOR EVEN TERMINAL/SIDE Table 12. Package Dimensions Controlling Dimension: mm Symbol Millimeters Min Nom A — 0.85 A1 0.00 0.01 b 0.18 0. ...
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... Si4133W Document Change List Revision 1.0 to Revision 1.1 Table 5 on page 8 RFOUT and IFOUT Output Power Level specifications have been updated Note 1 RF2 spec changed to 1.5 GHz 30 Rev. 1.1 ...
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... Notes: Rev. 1.1 Si4133W 31 ...
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... Si4133W Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free: 1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...