SI4133W-BM Silicon Laboratories Inc, SI4133W-BM Datasheet - Page 16

• Manufacturer Part Number: SI4133W-BM
• Description: IC SYNTHESIZER RF DUALBAND 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133W-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.6GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1115

Si4133W
Functional Description
The Si4133W is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for W-CDMA
communications applications. The Si4133W may be
operated continuously over a wide ambient temperature
range of –25 to +85
The Si4133W has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4133W suitable for use in demanding wireless
communications applications. Also integrated are phase
detectors, loop filters, and reference and output
frequency dividers. The IC is programmed through a
three-wire serial interface.
Two PLLs are provided for dual-band RF synthesis.
These RF PLLs are multiplexed so that only one PLL is
active at a given time, as determined by the setting of
an internal register. The active PLL is the last one
written. The center frequency of the VCO in each PLL is
set either by the internally bonded inductance within the
package or by the value of an external inductance. For
example, the Si4133W can have the RF2 center
frequency set by an external inductor, while the RF1
center frequency is fixed by the inductance of internal
bond wires. Inaccuracies in these inductances are
compensated for by the self-tuning algorithm. The
Si4133W executes the algorithm following powerup or
following
frequency.
The RF2 PLL, whose frequency is set through an
external inductance, can adjust the output frequency by
±5% of its VCO’s center frequency when active.
Because the two VCOs can be set to have widely
separated center frequencies, the RF output can be
programmed to service two widely separated frequency
bands by programming the corresponding N-Divider.
The Si4133W has the RF1 VCO optimized to operate
from 2.3 to 2.6 GHz, while the RF2 VCO is optimized to
have its center frequency set between 750 MHz and
1.7 GHz.
One PLL is provided for IF synthesis. The center
frequency of this circuit’s VCO is set by connection of an
external inductance. The PLL can adjust the IF output
frequency by ±5% of the VCO center frequency.
Inaccuracies in the value of the external inductance are
compensated for by the Si4133W’s proprietary self-
tuning algorithm. This algorithm is initiated each time
the PLL is powered-up (by either the PWDNB pin or by
software) and/or each time a new output frequency is
programmed.
The IF VCO can have its center frequency set as low as
16
a
change
o
C.
in
the
programmed
output
Rev. 1.1
526 MHz and as high as 952 MHz. An IF output divider
is provided to divide down the IF output frequencies, if
needed. The divider is programmable, capable of
dividing by 1, 2, 4, or 8.
The unique PLL architecture used in the Si4133W
produces settling (lock) times comparable in speed to
fractional-N architectures without suffering the high
phase noise or spurious modulation effects often
associated with those designs.
Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial interface.
The Si4133W is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SENB is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SENB into the internal data register
addressed in the address field. The serial interface is
disabled when SENB is high.
Table 11 on page 21 summarizes the data register
functions and addresses. The internal shift register will
ignore any leading bits before the 22 required bits.
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF2 output frequencies
±5% of the center frequencies of their VCOs. The RF1
PLL has a fixed operating range due to the inductance
set by the internally bonded wires. Each center
frequency for IF and RF2 PLLs is established by the
value of the total inductance (internal and/or external)
connected to the respective VCO. Manufacturing
tolerances of ±10% for the external inductances are
acceptable.
inaccuracies in each inductance by executing a self-
tuning algorithm following PLL powerup or following a
change in the programmed output frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package needs to be
considered
inductance. The total inductance (L
each VCO is the sum of the external inductance (L
and the package inductance (L
nominal capacitance (C
inductance, and the center frequency is as follows:
in
The
determining
Si4133W
NOM
) in parallel with the total
PKG
will
the
). Each VCO has a
TOT
compensate
correct
) presented to
external
EXT
for
)