SI4133W-BM Silicon Laboratories Inc, SI4133W-BM Datasheet - Page 17

• Manufacturer Part Number: SI4133W-BM
• Description: IC SYNTHESIZER RF DUALBAND 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4133W-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.6GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2.6GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1115

or
Table 6 summarizes the characteristics of each VCO.
As a design example, suppose synthesizing IFs in a
30 MHz band between 735 MHz and 765 MHz is
desired. The center frequency should be defined as
midway between the two extremes, or 750 MHz. The
PLL will be able to adjust the VCO output frequency
±5% of the center frequency, or ±37.5 MHz of 750 MHz
(i.e., from approximately 713 to 788 MHz). The IF VCO
has a C
two digits) in parallel with this capacitance will yield the
desired center frequency. An external inductance of
5.0 nH should be connected between IFLA and IFLB, as
shown in Figure 14. This, in addition to 1.6 nH of
package inductance, will present the correct total
inductance to the VCO. In manufacturing, the external
inductance can vary ±10% of its nominal value and the
Si4133W will correct for the variation with the self-tuning
algorithm.
VCO Fcen Range
RF2
Figure 14. External Inductance Connection
IF
Table 6. Si4133W-BM VCO Characteristics
NOM
789 1619
526
Min
f
CEN
of 6.8 pF. A 6.6 nH inductance (correct to
(MHz)
f
CEN
=
Max
952
----------------------------------------------------------------------
2π
=
L
L
(
---------------------------------------------
2π L
Cnom
PKG
PKG
L
2
2
(pF)
5.1
6.8
PKG
TOT
+
1
1
L
Lpkg
EXT
(nH)
⋅
1.6
1.6
C
NOM
) C
⋅
NOM
0.29
Lext Range
Min
2.5
(nH)
L
11.9
Max
EXT
6.4
Rev. 1.1
For more information on designing the external trace
inductors, please refer to Application Note 31.
Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately
following power-up of a PLL or, if the PLL is already
powered, following a change in its programmed output
frequency. This algorithm attempts to tune the VCO so
that its free-running frequency is near the desired output
frequency. In doing so, the algorithm will compensate
for manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It will also
reduce the frequency error for which the PLL must
correct to get the precise desired output frequency. The
self-tuning algorithm will leave the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL will complete frequency locking,
eliminating any remaining frequency error. Thereafter, it
will maintain frequency-lock, compensating for effects
caused by temperature and supply voltage variations.
The Si4133W’s self-tuning algorithm will compensate
for component value errors at any temperature within
the specified temperature range. However, the ability of
the PLL to compensate for drift in component values
that occur after self-tuning is limited. For external
inductances with temperature coefficients around
±150 ppm/
changes in temperature of –50 to +80
temperature at which it initialized lock.
If the PLL is regularly powered down or the frequency is
periodically reprogrammed, then this temperature range
is of no concern because the VCO lock will be
reinitiated. Lock-detect bar (LDETB) may be monitored
on the AUXOUT pin for an indication that the PLL is
about to run out of locking capability. (See “Auxiliary
Output (AUXOUT)”
LDETB signal will be low after self-tuning has completed
but will rise when either the IF or RF PLL nears the limit
of its compensation range. LDETB will also be high
when either PLL is executing the self-tuning algorithm.
The output frequency will still be locked when LDETB
goes high, but the PLL will eventually lose lock if the
temperature continues to change in the same direction.
Therefore, if LDETB goes high, both the IF and RF
PLLs should promptly be re-tuned by initiating the self-
tuning algorithm.
o
C, the PLL will be able to maintain lock for
for how to select LDETB.) The
Si4133W
o
C from the
17