MC88915FN70R2 Freescale Semiconductor, MC88915FN70R2 Datasheet - Page 5

• Manufacturer Part Number: MC88915FN70R2
• Description: IC DRIVER CLK PLL 70MHZ 28-PLCC
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MC88915FN70R2

• Pll: Yes
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:8
• Differential - Input:output: No/No
• Frequency - Max: 70MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 70MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC88915FN70R2TR

General AC Specification Notes
TIMING SOLUTIONS
BR1333 — Rev 6
1. Several specifications can only be measured when the
4. A 1 M resistor tied to either Analog V CC or Analog GND
MC88915 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88915 units were fabricated
with key transistor properties intentionally varied to
create a 14 cell designed experimental matrix. IC
performance was characterized over a range of transistor
properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area.
Response Surface Modeling (RSM) techniques were
used to relate IC performance to the CMOS transistor
properties over operation voltage and temperature. IC
Performance to each specification and fab variation were
used in conjunction with Yield Surface Modeling
specifications within those which are to be guaranteed by
as shown in Figure 2 is required to ensure no jitter is
present on the MC88915 outputs. This technique causes
a phase offset between the SYNC input and the output
connected to the FEEDBACK input, measured at the
input pins. The t PD spec describes how this offset varies
with process, temperature, and voltage. The specs were
arrived at by measuring the phase relationship for the 14
FREQ_SEL
) methodology to set performance limits of ATE testable
Level
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2
Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4
Feedback
Output
2X_Q
2X_Q
Output
88915
2X_Q
Q/2
Q/2
Q5
Q5
Figure 1. MC68040 P–Clock Input Termination Scheme
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
R s
Frequency Range (MHZ)
R s = Z o – 7
Allowable SYNC Input
Z O (CLOCK TRACE)
(YSM
5
2. These two specs (t RlSE/FALL and t PULSE Width 2X_Q
3. The wiring Diagrams and written explanations in Figure 5
statistical characterization. In this way all units passing
the ATE test will meet or exceed the non–tested
specifications limits.
output) guarantee that the MC88915 meets the 25 MHz
68040 P–Clock input specification (at 50 MHz). For these
two specs to be guaranteed by Motorola, the termination
scheme shown below in Figure 1 must be used.
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a
180 phase shift between the SYNC input and the “Q”
outputs. Table 1 below summarizes the allowable SYNC
frequency range for each possible configuration.
lots described in note 1 while the part was in
phase–locked operation. The actual measurements were
made with a 10 MHz SYNC input (1.0 ns edge rate from
0.8 V – 2.0 V) with the Q/2 output fed back. The phase
measurements were made at 1.5 V. The Q/2 output was
terminated at the FEEDBACK input with 100 to V CC and
100
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAXSpec)
20 to (2X_Q FMAXSpec)
R p
Corresponding VCO
Frequency Range
to ground.
R p = 1.5 Z o
P–Clock
68040
Input
to Rising SYNC Edge
Phase Relationships
of the “Q” Outputs
180
180
0
0
0
0
0
0
MC88915
MOTOROLA