SI5321-G-BC Silicon Laboratories Inc, SI5321-G-BC Datasheet - Page 13
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SI5321-G-BC
Manufacturer Part Number
SI5321-G-BC
Description
IC PREC CLOCK MULTIPLIER 63CBGA
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Datasheet
1.SI5321-H-GL.pdf
(34 pages)
Specifications of SI5321-G-BC
Package / Case
63-CBGA
Pll
Yes
Input
LVTTL
Output
CML
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
Yes/Yes
Frequency - Max
2.8GHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
2.4GHz
Mounting Style
SMD/SMT
Description/function
The is a precision clock multiplier designed to exceed the requirements of high speed communication systems
Operating Supply Voltage
3.3 V
Operating Temperature Range
- 55 C to + 150 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1274
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI5321-G-BC
Manufacturer:
SILICON
Quantity:
5
Company:
Part Number:
SI5321-G-BC
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI5321-G-BC
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 11 and BWBOOST = 0; FXDDELAY = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT RMS Jitter Generation
FEC[2:0] = 001, 010, 100,101, 110, 111
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 001, 010, 100,101, 110, 111
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 12800 Hz Bandwidth
(BWSEL[1:0] = 11 and BWBOOST = 1; FXDDELAY = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Acquisition Time
Notes:
DD33
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
= 3.3 V ±5%, TA = –20 to 85 °C)
of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
Parameter
J
J
J
J
J
J
Symbol
J
GEN(RMS)
GEN(RMS)
GEN(RMS)
GEN(PP)
GEN(PP)
GEN(PP)
TOL(PP)
F
F
T
J
J
BW
BW
AQ
P
P
Rev. 2.5
clock input and VALTIME = 0
CAL_ACTV low, with valid
RSTN/CAL high to
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
BW = 12,800 Hz
Test Condition
BW = 6400 Hz
f = 12800 Hz
< 12,800 Hz
f = 6400 Hz
f = 1280 Hz
f = 640 Hz
< 6400 Hz
f = 128 Hz
f = 64 Hz
1000
Min
100
500
10
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
12800
6400
0.05
0.05
Typ
300
1.0
0.4
1.0
.45
9.3
4.1
8.0
4.0
.85
.35
6.8
3.4
—
—
—
—
—
—
Si5321
Max Unit
13.0
20.0
11.0
350
1.3
.55
1.5
0.7
6.0
7.5
0.1
1.2
.55
5.5
—
—
—
—
—
—
—
—
.1
ms
Hz
dB
Hz
dB
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
13