SI5321-G-BC Silicon Laboratories Inc, SI5321-G-BC Datasheet - Page 26
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SI5321-G-BC
Manufacturer Part Number
SI5321-G-BC
Description
IC PREC CLOCK MULTIPLIER 63CBGA
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Datasheet
1.SI5321-H-GL.pdf
(34 pages)
Specifications of SI5321-G-BC
Package / Case
63-CBGA
Pll
Yes
Input
LVTTL
Output
CML
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
Yes/Yes
Frequency - Max
2.8GHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
2.4GHz
Mounting Style
SMD/SMT
Description/function
The is a precision clock multiplier designed to exceed the requirements of high speed communication systems
Operating Supply Voltage
3.3 V
Operating Temperature Range
- 55 C to + 150 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1274
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI5321-G-BC
Manufacturer:
SILICON
Quantity:
5
Company:
Part Number:
SI5321-G-BC
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI5321-G-BC
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si5321
26
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
Pin #
H5
H8
B3
A3
A2
B2
logic low state if the input is not driven from an external source.
FRQSEL[0]
FRQSEL[1]
FRQSEL[2]
Pin Name
FEC[0]
FEC[1]
FEC[2]
Table 10. Si5321 Pin Descriptions (Continued)
I/O
I*
I*
Signal Level
LVTTL*
LVTTL*
Rev. 2.5
Clock Output Frequency Range Select.
Select the frequency range of the clock output, CLK-
OUT. (See Table 3 on page 7.)
001 = 19 MHz Frequency Range.
000 = 39 MHz Frequency Range.
100 = 78 MHz Frequency Range.
010 = 155 MHz Frequency Range.
101 = 311 MHz Frequency Range.
011 = 622 MHz Frequency Range.
110 = 1.25 GHz Frequency Range.
111 = 2.5 GHz Frequency Range.
FEC Selection.
Enables or disables scaling of the input-to-output
frequency multiplication factor for FEC clock rate
compatibility.
The frequency of the CLKOUT output is a multiple of
the frequency of the CLKIN input. Selecting the
clock input range, the clock output range, and the
FEC scaling factor sets the input-to-output fre-
quency multiplication factor. The clock output fre-
quency is selected using the FRQSEL[2:0] pins. The
clock input frequency is selected using the INFRQ-
SEL[2:0] pins. Scaling factors of 255/238, 238/255,
255/237, 237/255, 66/64, or 64/66 may be selected
for FEC operation using the FEC[2:0] control pins as
indicated below. Scaling factors of 255/237, 237/
255, 66/64, or 64/66 require that the input clock rate
be in the 155 MHz or higher range.
000 = No FEC scaling.
001 = 255/238 FEC scaling.
010 = 238/255 FEC scaling.
011 = Reserved.
100 = 255/237 FEC scaling (155 MHz or higher
input clock range required).
101 = 237/255 FEC scaling (155 MHz or higher
input clock range required).
110 = 66/64 FEC scaling (155 MHz or higher input
clock range required).
111 = 64/66 FEC scaling (155 MHz or higher input
clock range required).
Description