PCA8565TS/1,118 NXP Semiconductors, PCA8565TS/1,118 Datasheet
PCA8565TS/1,118
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935272132118
PCA8565TS-T
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PCA8565TS/1,118 Summary of contents
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PCA8565 Real time clock/calendar Rev. 02 — 16 June 2009 1. General description The PCA8565 is a CMOS consumption. A programmable clock output, interrupt output and voltage-low detector are also provided. All address and data are transferred serially via a ...
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... NXP Semiconductors 4. Ordering information Table 1. Type number PCA8565TS PCA8565BS 5. Marking Table 2. Type number PCA8565TS PCA8565BS PCA8565_2 Product data sheet Ordering information Package Name Description TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm HVSON10 plastic thermal enhanced very thin small outline package ...
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... NXP Semiconductors 6. Block diagram OSCI OSCILLATOR 32.768 kHz OSCO MONITOR POWER-ON RESET WATCH DOG 2 SDA I C INTERFACE SCL PCA8565 Fig 1. Block diagram of PCA8565 PCA8565_2 Product data sheet DIVIDER CONTROL 00h Control_1 01h Control_2 0Dh CLKOUT_control TIME 02h Seconds 03h Minutes 04h ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning OSCI 1 OSCO 2 PCA8565TS INT 001aaj754 Top view. For mechanical details see Fig 2. Pin configuration of PCA8565TS (TSSOP8) 7.2 Pin description Table 3. Symbol OSCI OSCO n.c. INT V SS SDA SCL CLKOUT V DD [1] The die paddle (exposed pad) is wired to V ...
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... NXP Semiconductors 8. Device protection diagram Fig 4. 9. Functional description The PCA8565 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, a ...
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... NXP Semiconductors 9.1 Register overview Table 4. Register overview and control bits default values Bit positions labeled as - are not implemented. Bit positions labeled as N should always be written with logic 0. Reset values are shown in Table 7. Address Register name Control registers 00h Control_1 01h ...
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... NXP Semiconductors 9.2 Control registers 9.2.1 Register Control_1 Table 5. Bit Symbol 7 TEST1 STOP TESTC [1] Default value. [2] Bits labeled as N should always be written with logic 0. 9.2.2 Register Control_2 Table 6. Bit Symbol TI_TP AIE 0 TIE [1] Bits labeled as N should always be written with logic 0. ...
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... NXP Semiconductors 9.3 Reset The PCA8565 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I other registers are set according to Table 7. Address Register name 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh ...
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... NXP Semiconductors Table 9. Seconds value in decimal Table 10. Bit Symbol MINUTES [1] Values shown in decimal. Table 11. Bit Symbol HOURS [1] Values shown in decimal. Table 12. Bit Symbol DAYS [1] The PCA8565 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. ...
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... NXP Semiconductors Table 14. [1] Day Sunday Monday Tuesday Wednesday Thursday Friday Saturday [1] Definition may be re-assigned by the user. Table 15. Bit Symbol MONTHS [1] This bit may be re-assigned by the user. [2] This bit is toggled when the years register overflows from 99 to 00. [3] Values shown in decimal. ...
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... NXP Semiconductors Table 17. Bit Symbol YEARS [1] Values shown in decimal. 9.5 Data flow Figure 5 Fig 5. If the time registers are written or read by making individual access to the chip, then there is the risk that the time will increment between accesses. This has to be avoided by stopping the increment of the time circuit ...
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... NXP Semiconductors 3. Send a RESTART condition or STOP followed by START. 4. Send the slave address for read (A3h). 5. Read the register Seconds. 6. Read the register Minutes. 7. Read the register Hours. 8. Read the register Days. 9. Read the register Weekdays. 10. Read the register Months_century. 11. Read the register Years. ...
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... NXP Semiconductors 9.6.1 Alarm registers Table 18. Bit Symbol 7 AE_M MINUTE_ALARM [1] Default value. [2] Values shown in decimal. Table 19. Bit Symbol 7 AE_H HOUR_ALARM [1] Default value. [2] Values shown in decimal. Table 20. Bit Symbol 7 AE_D DAY_ALARM [1] Default value. [2] Values shown in decimal. Table 21. Bit Symbol 7 AE_W WEEKDAY_ALARM [1] Default value. ...
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... NXP Semiconductors Alarm registers which have their bit AE_x at logic 1 are ignored. Table 23 flags is made by a write command; therefore bits and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. Fig 7. To prevent the timer flags being overwritten while clearing AF, a logical AND is performed during a write access. Writing a logic 1 will cause the fl ...
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... NXP Semiconductors 9.7.1 Register Timer_control Table 24. Bit Symbol TD[1:0] [1] Default value. [2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set The timer register is an 8-bit binary countdown timer enabled and disabled via the bit TE in register Timer_control. The source clock for the timer is also selected by the TD[1:0] in register Timer_control ...
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... NXP Semiconductors TE COUNTDOWN COUNTER from interface: clear TF set alarm flag, AF from interface: clear AF When bits TIE and AIE are disabled, pin INT will remain high-impedance. Fig 8. Interrupt scheme 9.8.2 Bits TIE and AIE These bits activate or deactivate the generation of an interrupt when asserted respectively ...
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... NXP Semiconductors Table 27. Bit Symbol FD[1:0] [1] Default value. 9.10 Voltage-low detector The PCA8565 has an on-chip voltage-low detector. When V the Seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag is cleared using the interface. Bit VL is intended to detect the situation when V battery operation ...
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... NXP Semiconductors The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided down into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0 (STOP must be cleared before the pre-scaler can operate again). ...
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... NXP Semiconductors The STOP bit function will not affect the output of 32.768 kHz but will stop 1.024 kHz and 1 Hz. The lower two stages of the prescaler (F is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between zero and one 8.192 kHz cycle (see Fig 11 ...
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... NXP Semiconductors The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by the prescaler bits F (see Table 9.13 Power-On Reset (POR) override The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device ...
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... NXP Semiconductors 10. Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER / RECEIVER Fig 15. System configuration 10.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 2 10.5 I C-bus protocol 10.5.1 Addressing Before any data is transmitted on the I addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The PCA8565 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line ...
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... NXP Semiconductors acknowledgement from slave S SLAVE ADDRESS 0 A R/W Fig 19. Master reads after setting word address (write word address; read data) Fig 20. Master reads slave immediately after first byte (read mode) 10.5.3 Interface watchdog timer During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface, the PCA8565 has a built in watchdog timer ...
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... NXP Semiconductors a. Correct data transfer: read or write b. Incorrect data transfer: read or write Fig 21. Interface watchdog timer PCA8565_2 Product data sheet WD timer WD timer running data valid slave address data time running time counters frozen counters WD timer data valid slave address data time ...
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... NXP Semiconductors 11. Limiting values Table 29. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot T amb T stg V ESD I lu According to the NXP store and transport conditions (document SNW-SQ-623 ) the devices have to be [1] stored at a temperature +45 C and a humidity [2] Pass level; Human Body Model (HBM) according to JESD22-A114. ...
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... NXP Semiconductors 12. Characteristics 12.1 Static characteristics Table 30. Static characteristics specified. Symbol Parameter Supplies V supply voltage DD V low voltage low I supply current DD Inputs V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI C input capacitance i Outputs I LOW-level output current ...
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... NXP Semiconductors 1 1.0 0 Timer = 1 minute; CLKOUT disabled. amb Fig 22 function 1 1.0 0 Timer = 1 minute; CLKOUT = 32 kHz. DD Fig 24 function of temperature DD PCA8565_2 Product data sheet mld970 (V) DD Fig 23. I mld972 frequency deviation (ppm) 80 120 160 Fig 25. Frequency deviation as a function of V Rev. 02 — 16 June 2009 Real time clock/calendar 1 ...
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... NXP Semiconductors 12.2 Dynamic characteristics Table 31. Dynamic characteristics specified. Symbol Parameter Oscillator C integrated load capacitance L(itg relative oscillator frequency variation osc osc Quartz crystal parameters (f = 32.768 kHz) R series resistance s C load capacitance L C trimmer capacitance trim CLKOUT output duty cycle on pin CLKOUT ...
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... NXP Semiconductors SDA SCL SDA Fig 26. I PCA8565_2 Product data sheet t t BUF LOW t HD;STA C-bus timing waveforms Rev. 02 — 16 June 2009 PCA8565 Real time clock/calendar HD;DAT t HIGH t SU;STA © NXP B.V. 2009. All rights reserved. SU;DAT t SU;STO mga728 ...
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... NXP Semiconductors 13. Application information Fig 27. Application diagram of PCA8565 13.1 Quartz frequency adjustment 13.1.1 Method 1: fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz ...
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... NXP Semiconductors 14. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 0. terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 34. Acronym BCD CDM CMOS HBM MSB MSL PCB POR RC RTC SMD PCA8565_2 ...
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... Release date PCA8565_2 20090616 • Modifications The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors • Legal texts have been adapted to the new company name where appropriate • Added HVSON10 package • Added ESD and latch-up values • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Device protection diagram . . . . . . . . . . . . . . . . 5 9 Functional description . . . . . . . . . . . . . . . . . . . 5 9.1 Register overview . . . . . . . . . . . . . . . . . . . . . . . 6 9.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 9.2.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 7 9 ...