M41T83SQA6F STMicroelectronics, M41T83SQA6F Datasheet - Page 13

• Manufacturer Part Number: M41T83SQA6F
• Description: IC RTC SERIAL W/BATT SW 16QFN
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T83SQA6F

• Memory Size: 32B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Clock Format: 12Hr / 24Hr
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Supply Voltage Range: 3V To 5.5V
• Digital Ic Case Style: QFN
• No. Of Pins: 16
• Rohs Compliant: Yes
• For Use With: 497-10833 - DAUGHTER-CARD M41T83SQA6E QFN16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6887-2; M41T83SQA6F

M41T82-M41T83
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
●
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Doc ID 12578 Rev 12
Operation
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