ISL1220IUZ-T Intersil, ISL1220IUZ-T Datasheet - Page 15

• Manufacturer Part Number: ISL1220IUZ-T
• Description: IC RTC LP BATT BACK SRAM 10MSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Alarmr

Specifications of ISL1220IUZ-T

• Memory Size: 8B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL1220IUZ-TTR

receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
The ISL1220 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
THE MASTER
THE ISL1220
15
START
FIGURE 12. VALID DATA CHANGES, START AND STOP CONDITIONS
START
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
S
T
A
R
T
1
FIGURE 14. BYTE WRITE SEQUENCE
IDENTIFICATION
1
1
0
BYTE
1
STABLE
1 1 1
DATA
ISL1220
0
WRITE
A
C
K
CHANGE
DATA
0 0 0 0
ADDRESS
once again after successful receipt of an Address Byte. The
ISL1220 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
BYTE
STABLE
DATA
A
C
K
8
DATA
BYTE
HIGH IMPEDANCE
STOP
ACK
9
A
C
K
S
T
O
P
June 22, 2006
FN6315.0