M41ST84WMQ6F STMicroelectronics, M41ST84WMQ6F Datasheet
M41ST84WMQ6F
Specifications of M41ST84WMQ6F
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M41ST84WMQ6F Summary of contents
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NVRAM and supervisory functions Features ■ Automatic battery switchover and deselect – Power-fail deselect, V PFD – Switchover 2.50 V (nom ■ 400 kHz I C serial interface ■ 3.0/3.3 V operating ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41ST84W 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41ST84W List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The M41ST84W serial real-time clock is built in a low power CMOS SRAM process. It has a 64-byte memory space with 44 bytes of NVRAM and 20 memory-mapped RTC registers. The RTC registers are configured in binary ...
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M41ST84W Figure 1. Logic diagram Table 1. Signal names XI XO IRQ/FT/OUT PFI PFO RST RSTIN SCL SDA SQW WDI BAT BAT XI XO SCL SDA M41ST84W RSTIN WDI PFI V ...
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Description Figure 2. 16-pin SOIC connections RST WDI RSTIN PFO V BAT V SS Figure 3. Block diagram SDA SCL XI Crystal XO WDI BAT V SS RSTIN PFI 1. Open drain output 8/ ...
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M41ST84W Figure 4. Hardware hookup Unregulated Voltage User-supplied crystal Regulator M41ST84W 32KHz (1) XTAL XO SDA SCL WDI RSTIN V BAT PFI V SS Doc ID 7530 Rev 9 IRQ/FT/OUT ...
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Operating modes 2 Operating modes The M41ST84W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can ...
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M41ST84W Accordingly, the following bus conditions have been defined: 2.1.1 Bus not busy Both data and clock lines remain high. 2.1.2 Start data transfer A change in the state of the data line, from high to low, while the clock ...
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Operating modes Figure 5. Serial bus data transfer sequence CLOCK DATA START CONDITION Figure 6. Acknowledgement sequence START SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 12/36 DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED 1 ...
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M41ST84W Figure 7. Bus timing requirements sequence SDA tBUF SCL P S Table 2. AC characteristics Symbol SCL clock frequency f SCL Time the bus must be free before a new transmission can t BUF start t SDA and SCL ...
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Operating modes 2.2 READ mode In this mode the master reads the M41ST84W slave after setting the slave address (see Figure 8). Following the WRITE mode control bit (R and the acknowledge bit, the word address ‘An’ is ...
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M41ST84W Figure 9. READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 10. Alternate READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS WORD S ADDRESS (An) SLAVE ADDRESS ...
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Operating modes 2.3 WRITE mode In this mode the master transmitter transmits to the M41ST84W slave receiver. Bus protocol is shown in Figure is placed on the bus and indicates to the addressed device that word address An will follow ...
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M41ST84W 3 Clock operation The eight byte clock register (see read the date and time from the clock binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Note: A ...
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Clock operation ® Table 3. TIMEKEEPER register map Address D7 D6 00h 0.1 seconds 01h ST 10 seconds 02h 0 10 minutes 03h CEB CB 04h TR 0 05h 0 0 06h 0 0 07h 10 years 08h OUT FT ...
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M41ST84W 3.3 Calibrating the clock The M41ST84W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/–35 ppm (parts per million) oscillator frequency error at 25 Calibration circuit is ...
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Clock operation Figure 12. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 Figure 13. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 20/ –T ) ...
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M41ST84W 3.4 Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, ...
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Clock operation Figure 15. Backup mode alarm waveform PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT 3.5 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. ...
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M41ST84W pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (Bit D7; Register 0Fh). The watchdog function is automatically disabled upon power-up and the ...
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Clock operation 3.8 Reset input (RSTIN) The M41ST84W provides an independent input which can generate an output reset. The duration and function of this reset is identical to a reset generated by a power cycle. and Figure 16 illustrate the ...
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M41ST84W 3.10 Century bit Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a “1” will cause CB to toggle, either from a “0” to “1” or ...
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Clock operation 3.14 Initial power-on defaults Upon initial application of power to the device, the following register bits are set to a '0' state: watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' ...
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M41ST84W 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
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DC and AC parameters 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived ...
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... Load capacitors are integrated within the M41ST84W. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, tuning fork type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at http://www ...
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DC and AC parameters Figure 18. Power down/up mode AC waveforms PFD (max) V PFD (min PFO INPUTS RECOGNIZED RST OUTPUTS VALID (PER CONTROL INPUT) Table 14. Power down/up AC characteristics Symbol (2) t ...
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M41ST84W 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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Package mechanical data Figure 20. Carrier tape for SO16 package T TOP COVER TAPE K 0 Table 16. Carrier tape dimensions for SO16 package Package 1.50 16.00 1.75 SO16 +0.10/ ±0.30 ±0.10 –0.00 32/ ...
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M41ST84W Figure 21. Reel schematic D A Full radius Table 17. Reel dimensions for 16 mm carrier tape - SO16 package A B (max) (min) 330 mm 1.5 mm (13-inch) Note: The dimensions given in parameters. 40mm min. Access hole ...
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Part numbering 7 Part numbering Table 18. Ordering information scheme Example: Device type M41ST Supply voltage and write protect voltage (1) = 2.7 to 3.6 V; 2.55 V ≤ V 84W = V CC Package MQ = SO16 Temperature range ...
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M41ST84W 8 Revision history Table 19. Document revision history Date Revision Aug-2000 1 First issue 24-Aug-2000 1.2 Block diagram added 08-Sep-2000 1.3 SO16 package measures change 18-Dec-2000 2 Reformatted, TOC added, and PFI input leakage current added Addition of t ...
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