ISL12025IBZ Intersil, ISL12025IBZ Datasheet

IC RTC/CALENDAR EEPROM 8-SOIC

ISL12025IBZ

Manufacturer Part Number
ISL12025IBZ
Description
IC RTC/CALENDAR EEPROM 8-SOIC
Manufacturer
Intersil
Type
Clock/Calendar/Supervisor/EEPROMr
Datasheets

Specifications of ISL12025IBZ

Memory Size
4K (512 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Bus Type
Serial (I2C)
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
8
Mounting
Surface Mount
Clock Format
HH
Clock Ic Type
RTC
Interface Type
I2C, Serial
Memory Configuration
512 X 8
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Real-Time Clock/Calendar with EEPROM
The ISL12025 device is a low power real-time clock with
timing and crystal compensation, clock/calender, 64-bit
unique ID, power-fail indicator, two periodic or polled alarms,
intelligent battery backup switching, CPU Supervisor and
integrated 512 x 8-bit EEPROM, in a 16 Bytes per page
format.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Add “-T” suffix for tape and reel.
Pinouts
ISL12025IBZ 12025IBZ
ISL12025IVZ 2025IVZ
NUMBER
(Note)
PART
RESET
MARKING
GND
PART
V
X1
X2
V
BAT
DD
X1
X2
(8 LD TSSOP)
VOLTAGE
(8 LD SOIC)
1
2
3
4
V
TOP VIEW
TOP VIEW
1
2
3
4
ISL12025
ISL12025
2.63V
2.63V
RESET
®
1
8
7
6
5
-40 to +85 8 Ld SOIC
-40 to +85 8 Ld TSSOP M8.173
RANGE
8
7
6
5
TEMP.
Data Sheet
(°C)
SCL
SDA
GND
RESET
V
V
SCL
SDA
DD
BAT
PACKAGE
(Pb-Free)
1-888-INTERSIL or 1-888-468-3774
M8.15
DWG.
PKG.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
#
New Features
*I
2
Features
• Real-Time Clock/Calendar
• 64-bit Unique ID
• Two Non-Volatile Alarms
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
• 512 x 8 Bits of EEPROM
• High Reliability
• I
• 800nA Battery Supply Current
• Package Options
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
C is a Trademark of Philips. Copyright Intersil Americas Inc. 2006. All Rights Reserved
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
- Settable on the Second, Minute, Hour, Day of the Week,
- Repeat Mode (periodic interrupts)
- Internal Feedback Resistor and Compensation
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of Block Lock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
- 400kHz Data Transfer Rate
- 8 Ld SOIC and 8 Ld TSSOP Packages
2
C* Interface
Day, or Month
Capacitors
October 18, 2006
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
ISL12025
FN6371.1

Related parts for ISL12025IBZ

ISL12025IBZ Summary of contents

Page 1

... PART V RANGE RESET (Note) MARKING VOLTAGE (°C) ISL12025IBZ 12025IBZ 2.63V - SOIC ISL12025IVZ 2025IVZ 2.63V - TSSOP M8.173 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 2

Block Diagram X1 32.768kHz X2 Control Serial SCL Decode Interface Logic Decoder SDA 8 RESET Pin Descriptions PIN NUMBER SOIC TSSOP SYMBOL The X1 pin is the input of an inverting amplifier and is intended to be ...

Page 3

Absolute Maximum Ratings Voltage SCL, SDA, and RESET pins DD BAT (respect to ground ...

Page 4

Watchdog Timer/Low Voltage Reset Parameters SYMBOL PARAMETER t V Detect to RESET LOW RPD DD t Power-up Reset Time-Out Delay PURST V Minimum V for Valid RESET RVALID DD Output V ISL12025-4.5A Reset Voltage RESET Level ISL12025 Reset Voltage Level ...

Page 5

Serial Interface (I C) Specifications SYMBOL PARAMETER t Clock LOW Time LOW t Clock HIGH Time HIGH t START Condition Setup Time SU:STA t START Condition Hold Time HD:STA t Input Data Setup Time SU:DAT t Input Data Hold ...

Page 6

Timing Diagrams SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) SCL 8TH BIT OF LAST BYTE SDA t RSP SCL SDA RESET START NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (t V RESET V ...

Page 7

Typical Performance Curves 4.00 BSW = 3.50 SCL,SDA pullups = 0V 3.00 2.50 2.00 1.50 SCL,SDA pullups = Vbat 1.00 0.50 BSW = 0.00 1.8 2.3 2.8 3.3 3.8 Vbat (V) FIGURE 5. I ...

Page 8

Description The ISL12025 device is a Real-Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM configured in 16 Bytes per page format, oscillator compensation, CPU Supervisor (Power-on Reset, Low Voltage Sensing and Watchdog Timer) and battery backup switch. ...

Page 9

... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information see the “ ...

Page 10

DW: Day of the Week Register This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of ...

Page 11

NO other value written to that bit. X indicates the bits are set according to the product variation (see device ordering information). * indicates set at the factory, read-only) REG ADDR. TYPE NAME ...

Page 12

Alarm Registers (Non-Volatile) Alarm0 and Alarm1 The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm ...

Page 13

A range from -30ppm to +30ppm can be represented by using the three bits previously explained. TABLE 4. DIGITAL TRIMMING REGISTERS DTR REGISTER ESTIMATED FREQUENCY DTR2 DTR1 DTR0 ...

Page 14

... Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil RTC device for years. Another option is to use a SuperCap for applications where V for month. See the “Application Section” on page 21 for more information ...

Page 15

Standard Mode Power Switchover • Normal Operating Mode ( Battery Backup Mode BAT To transition from the BAT following conditions must be met: - Condition 1: V < ...

Page 16

TABLE 6. WD1 WD0 Watchdog Timer Restart The Watchdog Timer is started by a falling edge of SDA when the SCL line is high (START condition). The start signal restarts the watchdog ...

Page 17

SCL SDA SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER DEVICE IDENTIFIER ARRAY CCR FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, ...

Page 18

SDA line. Following the Slave Byte is a two byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power-up the internal ...

Page 19

BYTES ADDRESS = 5 ADDRESS POINTER ENDS AT ADDR = 5 FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS SIGNALS FROM A THE MASTER R SLAVE T ADDRESS SDA BUS 1 ...

Page 20

Byte load completed by issuing STOP. Enter ACK Polling Issue START Issue Memory Array Slave Address Byte AFh (Read) or AEh (Write) NO ACK returned? YES NO Non-volatile write cycle complete. Continue command sequence? YES Continue normal Read or Write ...

Page 21

... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in increments of 10ppm. The default setting is 0ppm ...

Page 22

... Backup Battery Operation Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a supercapacitor for applications where V short periods of time ...

Page 23

A simple silicon or Schottky barrier diode can be used in series with V DD supercapacitor, which is connected to the V use Schottky diodes with very low leakages, <1µA desirable. Do not use the ...

Page 24

V (3.0V) BAT V DD (2.63V) V RESET V TRIP (2.2V) tPURST RESET I BAT (VDD POWER, V FIGURE 29. EXAMPLE RESET OPERATION IN MODE (3.0V) BAT V DD (2.63V) V RESET V TRIP (2.2V) tPURST ...

Page 25

Alarm Operation Examples Below are examples of both Single Event and periodic Interrupt Mode alarms. Example 1 – Alarm 0 set with single interrupt (IM = “0”) A single alarm will occur on January 1 at 11:30am. A. Set Alarm0 ...

Page 26

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...

Page 27

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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