ISL12025IBZ Intersil, ISL12025IBZ Datasheet - Page 20

IC RTC/CALENDAR EEPROM 8-SOIC

ISL12025IBZ

Manufacturer Part Number
ISL12025IBZ
Description
IC RTC/CALENDAR EEPROM 8-SOIC
Manufacturer
Intersil
Type
Clock/Calendar/Supervisor/EEPROMr
Datasheets

Specifications of ISL12025IBZ

Memory Size
4K (512 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Bus Type
Serial (I2C)
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
8
Mounting
Surface Mount
Clock Format
HH
Clock Ic Type
RTC
Interface Type
I2C, Serial
Memory Configuration
512 X 8
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SIGNALS FROM
SIGNALS FROM
THE MASTER
SDA BUS
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
THE SLAVE
FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE
ISSUE MEMORY ARRAY SLAVE
CYCLE COMPLETE. CONTINUE
AFH (READ) OR AEH (WRITE)
COMMAND SEQUENCE?
ENTER ACK POLLING
NON-VOLATILE WRITE
NORMAL READ OR
WRITE COMMAND
COMPLETED BY
ADDRESS BYTE
ISSUING STOP.
ISSUE START
BYTE LOAD
RETURNED?
SEQUENCE
CONTINUE
PROCEED
ACK
A
R
S
T
T
1
YES
YES
ADDRESS
SLAVE
20
1
1
1
NO
NO
1
A
C
K
ISSUE STOP
ISSUE STOP
DATA
O
S
P
T
ISL12025
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
Random Read
Random read operations allow the master to access any
location in the ISL12025. Prior to issuing the Slave Address
Byte with the R/W bit set to zero, the master must first
perform a “dummy” write operation.
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word
address bytes. After acknowledging receipt of each word
address byte, the master immediately issues another start
condition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the 8-bit data word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. See Figure 25 for the address,
acknowledge and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 25. The ISL12025 then goes
into Standby Power Mode after the stop and all bus activity
will be ignored until a start is detected. This operation loads
the new address into the address counter. The next Current
Address Read operation will read from the newly loaded
address. This operation could be useful if the master knows
the next address it needs to read, but is not ready for the
data.
Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space, the counter “rolls over” to the start of the
address space and the ISL12025 continues to output data
for each acknowledge received. See Figure 26 for the
acknowledge and data transfer sequence.
August 13, 2008
FN6371.3

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