ISL12025IBZ Intersil, ISL12025IBZ Datasheet - Page 5
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ISL12025IBZ
Manufacturer Part Number
ISL12025IBZ
Description
IC RTC/CALENDAR EEPROM 8-SOIC
Manufacturer
Intersil
Type
Clock/Calendar/Supervisor/EEPROMr
Specifications of ISL12025IBZ
Memory Size
4K (512 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Bus Type
Serial (I2C)
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
8
Mounting
Surface Mount
Clock Format
HH
Clock Ic Type
RTC
Interface Type
I2C, Serial
Memory Configuration
512 X 8
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Serial Interface (I
NOTES:
10. t
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
11. These are I
SYMBOL
3. RESET Inactive (no reset).
4. V
5. V
6. Bit BSW = 0 (Standard Mode), ATR=00h, V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V
9. Parameter is not 100% tested.
t
t
t
t
t
t
SU:STO
HD:STO
SU:STA
HD:STA
SU:DAT
HD:DAT
t
t
Cpin
HIGH
R
LOW
t
t
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
characterization and are not production tested.
Cb
WC
DH
WC
t
t
PU
R
F
IL
RESET
= V
is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
DD
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for
Read or Volatile Only Write
Output Data Hold Time
SDA and SCL Pin Capacitance
Non-Volatile Write Cycle Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive loading of SDA or SCL Total on-chip and off-chip
SDA and SCL Bus Pull-up Resistor
Off-chip
= 2.63V (VDD must be greater than V
x 0.1, V
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
2
IH
PARAMETER
C) Specifications
= V
DD
x 0.9, f
5
SCL
= 400kHz.
BAT
(Continued)
DD SR-
Measured at the 30% of V
crossing.
Measured at the 70% of V
crossing.
SCL rising edge to SDA falling
edge. Both crossing 70% of V
From SDA falling edge crossing
30% of V
crossing 70% of V
From SDA exiting the 30% to 70%
of V
crossing 30% of V
From SCL falling edge crossing
70% of V
30% to 70% of V
From SCL rising edge crossing
70% of V
crossing 30% of V
From SDA rising edge to SCL
falling edge. Both crossing 70% of
V
From SCL falling edge crossing
30% of V
30% to 70% of V
From 30% to 70% of V
From 70% to 30% of V
Maximum is determined by t
t
For Cb = 400pF, max is about
2kΩ~2.5kΩ.
For Cb = 40pF, max is about
15kΩ~20kΩ
F
DD
.
RESET
≥1.8V.
DD
.
specification must be followed.
window, to SCL rising edge
), V
DD
DD
DD
DD
CONDITIONS
, to SDA rising edge
, until SDA enters the
BAT
to SCL falling edge
to SDA entering the
ISL12025
= 0V.
DD
DD
DD
DD
DD
window.
window.
.
.
.
DD
DD
DD
DD
R
DD
and
.
(Note 12)
0.1xCb
0.1xCb
1300
20 +
20 +
MIN
600
600
600
100
600
600
10
0
0
1
TYP
12
(Note 12)
MAX
250
250
400
10
20
UNITS
ms
pF
pF
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
August 13, 2008
NOTES
FN6371.3
10
11
11
11
11