ISL12025IBZ Intersil, ISL12025IBZ Datasheet - Page 4

• Manufacturer Part Number: ISL12025IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12025IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Bus Type: Serial (I2C)
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Watchdog Timer/Low Voltage Reset Parameters
EEPROM SPECIFICATIONS
Serial Interface (I
SYMBOL
TIMING CHARACTERISTICS
V
Hysteresis SDA and SCL Input Buffer
V
SYMBOL
t
PURST
RVALID
t
RESET
t
t
t
WDO
RPD
RST
RSP
f
t
V
V
I
SCL
t
BUF
V
t
I
LO
AA
OL
IN
LI
IH
IL
V
Power-up Reset Time-Out Delay
Minimum V
Output
ISL12025-4.5A Reset Voltage
Level
ISL12025 Reset Voltage Level
ISL12025-3 Reset Voltage Level
ISL12025-2.7A Reset Voltage
Level
ISL12025-2.7 Reset Voltage Level
Watchdog Timer Period
Watchdog Timer Reset Time-Out
Delay
I
Time
EEPROM Endurance
EEPROM Retention
2
SDA and SCL Input Buffer LOW
Voltage
SDA and SCL Input Buffer HIGH
Voltage
Hysteresis
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must Be Free before
the Start of a New Transmission
DD
C Interface Minimum Restart
Detect to RESET LOW
PARAMETER
2
DD
PARAMETER
C) Specifications
for Valid RESET
4
32.768kHz crystal between X1 and X2
32.768kHz crystal between X1 and X2
Temperature ≤+75°C
SBIB = 1 (Under V
SBIB = 1 (Under V
SBIB = 1 (Under V
I
V
V
Any pulse narrower than the max
spec is suppressed.
SCL falling edge crossing 30% of
V
70% of V
SDA crossing 70% of V
STOP condition, to SDA crossing
70% of V
START condition.
OL
IN
IN
DD
= 4mA
= 5.5V
= 5.5V
, until SDA exits the 30% to
DD
DD
CONDITIONS
CONDITIONS
window.
during the following
ISL12025
DD
DD
DD
mode)
mode)
mode)
DD
during a
0.05xV
(Note 12)
0.7xV
2,000,000
1300
(Note 12)
MIN
-0.3
0
4.59
4.33
3.04
2.87
2.58
1.70
MIN
100
725
225
225
1.0
1.2
50
DD
DD
TYP
0.1
0.1
(Note 5)
TYP
4.64
4.38
3.09
2.92
2.63
1.75
500
250
750
250
250
V
(Note 12)
0.3xV
DD
MAX
(Note 12)
400
900
0.4
10
10
50
1.801
MAX
+ 0.3
4.69
4.43
3.14
2.97
2.68
400
775
275
275
DD
UNITS
kHz
µA
µA
ns
ns
ns
UNITS
Cycles
V
V
V
V
Years
ms
ms
ms
ms
ns
µs
V
V
V
V
V
V
s
August 13, 2008
NOTES
NOTES
FN6371.3
9