DS1342U+ Maxim Integrated Products, DS1342U+ Datasheet - Page 3

• Manufacturer Part Number: DS1342U+
• Description: IC RTC I2C W/ALARM 8USOP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Alarmr

Specifications of DS1342U+

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement t
AC ELECTRICAL CHARACTERISTICS
(V
CRYSTAL PARAMETERS
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time
Data Setup Time
Setup Time for a Repeated
START Condition
Rise Time of Both SDA and SCL
Signals
Fall Time for Both SDA and SCL
Signals
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line
I/O Capacitance
SCL Spike Suppression
Oscillator Stop Flag (OSF) Delay
Timeout Interval
Nominal Frequency
Series Resistance
Load Capacitance
CC
= +1.8V to +5.5V, T
Low-Current I
Limits at -40NC are guaranteed by design; not production tested.
Voltage referenced to ground.
Specified with I
Applies to CLKIN/INTA and SQW/INTB only.
The minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if SCL is
held low for t
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
nal) to bridge the undefined region of the falling edge of SCL.
The maximum t
met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
1250ns before the SCL line is released.
PARAMETER
PARAMETER
TIMEOUT
A
2
HD:DAT
C bus inactive. Oscillator operational, INTCN = 1, ECLK = 0.
= -40NC to +85NC, unless otherwise noted.) (Note 2, Figure 1)
.
need only be met if the device does not stretch the low period (t
SYMBOL
SYMBOL
t
t
TIMEOUT
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
f
HIGH
C
ESR
LOW
BUF
OSF
SCL
C
t
C
f
t
t
SP
I/O
O
R
F
B
L
2
(Note 6)
(Note 7)
(Notes 8, 9)
(Note 10)
(Note 11)
(Note 11)
(Note 11)
(Note 12)
(Note 13)
DS1341
DS1342
C RTCs for High-ESR Crystals
CONDITIONS
CONDITIONS
SU:DAT
0.1C
0.1C
20 +
20 +
MIN
MIN
100
1.3
0.6
1.3
0.6
0.6
0.6
25
0
LOW
RMAX
B
B
R to 250ns must then be
) of the SCL signal.
32.768
+ t
TYP
TYP
12.5
10
30
25
6
SU:DAT
IHMIN
MAX
MAX
of the SCL sig-
400
300
300
400
100
100
0.9
35
= 1000 + 250 =
UNITS
UNITS
kHz
kHz
ms
ms
kI
Fs
Fs
Fs
Fs
Fs
ns
Fs
ns
ns
Fs
pF
pF
ns
pF
3